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instruction-codes-ia32.h
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1 // Copyright 2014 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6 #define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7 
8 namespace v8 {
9 namespace internal {
10 namespace compiler {
11 
12 // IA32-specific opcodes that specify which assembly sequence to emit.
13 // Most opcodes specify a single instruction.
14 #define TARGET_ARCH_OPCODE_LIST(V) \
15  V(IA32Add) \
16  V(IA32And) \
17  V(IA32Cmp) \
18  V(IA32Test) \
19  V(IA32Or) \
20  V(IA32Xor) \
21  V(IA32Sub) \
22  V(IA32Imul) \
23  V(IA32Idiv) \
24  V(IA32Udiv) \
25  V(IA32Not) \
26  V(IA32Neg) \
27  V(IA32Shl) \
28  V(IA32Shr) \
29  V(IA32Sar) \
30  V(IA32Ror) \
31  V(SSEFloat64Cmp) \
32  V(SSEFloat64Add) \
33  V(SSEFloat64Sub) \
34  V(SSEFloat64Mul) \
35  V(SSEFloat64Div) \
36  V(SSEFloat64Mod) \
37  V(SSEFloat64Sqrt) \
38  V(SSECvtss2sd) \
39  V(SSECvtsd2ss) \
40  V(SSEFloat64ToInt32) \
41  V(SSEFloat64ToUint32) \
42  V(SSEInt32ToFloat64) \
43  V(SSEUint32ToFloat64) \
44  V(IA32Movsxbl) \
45  V(IA32Movzxbl) \
46  V(IA32Movb) \
47  V(IA32Movsxwl) \
48  V(IA32Movzxwl) \
49  V(IA32Movw) \
50  V(IA32Movl) \
51  V(IA32Movss) \
52  V(IA32Movsd) \
53  V(IA32Push) \
54  V(IA32StoreWriteBarrier)
55 
56 
57 // Addressing modes represent the "shape" of inputs to an instruction.
58 // Many instructions support multiple addressing modes. Addressing modes
59 // are encoded into the InstructionCode of the instruction and tell the
60 // code generator after register allocation which assembler method to call.
61 //
62 // We use the following local notation for addressing modes:
63 //
64 // M = memory operand
65 // R = base register
66 // N = index register * N for N in {1, 2, 4, 8}
67 // I = immediate displacement (int32_t)
68 
69 #define TARGET_ADDRESSING_MODE_LIST(V) \
70  V(MR) /* [%r1 ] */ \
71  V(MRI) /* [%r1 + K] */ \
72  V(MR1) /* [%r1 + %r2*1 ] */ \
73  V(MR2) /* [%r1 + %r2*2 ] */ \
74  V(MR4) /* [%r1 + %r2*4 ] */ \
75  V(MR8) /* [%r1 + %r2*8 ] */ \
76  V(MR1I) /* [%r1 + %r2*1 + K] */ \
77  V(MR2I) /* [%r1 + %r2*2 + K] */ \
78  V(MR4I) /* [%r1 + %r2*3 + K] */ \
79  V(MR8I) /* [%r1 + %r2*4 + K] */ \
80  V(M1) /* [ %r2*1 ] */ \
81  V(M2) /* [ %r2*2 ] */ \
82  V(M4) /* [ %r2*4 ] */ \
83  V(M8) /* [ %r2*8 ] */ \
84  V(M1I) /* [ %r2*1 + K] */ \
85  V(M2I) /* [ %r2*2 + K] */ \
86  V(M4I) /* [ %r2*4 + K] */ \
87  V(M8I) /* [ %r2*8 + K] */ \
88  V(MI) /* [ K] */
89 
90 } // namespace compiler
91 } // namespace internal
92 } // namespace v8
93 
94 #endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
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