41 const char PerfJitLogger::kFilenameFormatString[] =
"perfjit-%d.dump";
44 const int PerfJitLogger::kFilenameBufferPadding = 16;
47 PerfJitLogger::PerfJitLogger() : perf_output_handle_(
NULL), code_index_(0) {
48 if (!base::TimeTicks::KernelTimestampAvailable()) {
49 FATAL(
"Cannot profile with perf JIT - kernel timestamps not available.");
53 int bufferSize =
sizeof(kFilenameFormatString) + kFilenameBufferPadding;
54 ScopedVector<char> perf_dump_name(bufferSize);
55 int size =
SNPrintF(perf_dump_name, kFilenameFormatString,
56 base::OS::GetCurrentProcessId());
61 setvbuf(perf_output_handle_,
NULL, _IOFBF, kLogBufferSize);
67 PerfJitLogger::~PerfJitLogger() {
68 fclose(perf_output_handle_);
69 perf_output_handle_ =
NULL;
73 uint64_t PerfJitLogger::GetTimestamp() {
74 return static_cast<int64_t
>(
75 base::TimeTicks::KernelTimestampNow().ToInternalValue());
79 void PerfJitLogger::LogRecordedBuffer(Code* code, SharedFunctionInfo*,
80 const char*
name,
int length) {
81 DCHECK(code->instruction_start() == code->address() + Code::kHeaderSize);
84 const char* code_name =
name;
85 uint8_t* code_pointer =
reinterpret_cast<uint8_t*
>(code->instruction_start());
86 uint32_t code_size = code->is_crankshafted() ? code->safepoint_table_offset()
87 : code->instruction_size();
89 static const char string_terminator[] =
"\0";
93 code_load.
p.
total_size =
sizeof(code_load) + length + 1 + code_size;
95 code_load.
pid =
static_cast<uint32_t>(base::OS::GetCurrentProcessId());
96 code_load.
tid =
static_cast<uint32_t>(base::OS::GetCurrentThreadId());
98 code_load.
code_addr =
reinterpret_cast<uint64_t
>(code_pointer);
104 LogWriteBytes(
reinterpret_cast<const char*
>(&code_load),
sizeof(code_load));
105 LogWriteBytes(code_name, length);
106 LogWriteBytes(string_terminator, 1);
107 LogWriteBytes(
reinterpret_cast<const char*
>(code_pointer), code_size);
117 void PerfJitLogger::CodeDeleteEvent(
Address from) {
122 void PerfJitLogger::SnapshotPositionEvent(
Address addr,
int pos) {}
125 void PerfJitLogger::LogWriteBytes(
const char* bytes,
int size) {
126 size_t rv = fwrite(bytes, 1,
size, perf_output_handle_);
132 void PerfJitLogger::LogWriteHeader() {
138 header.
pad1 = 0xdeadbeef;
140 header.
pid = base::OS::GetCurrentProcessId();
142 static_cast<uint64_t
>(base::OS::TimeCurrentMillis() * 1000.0);
143 LogWriteBytes(
reinterpret_cast<const char*
>(&header),
sizeof(header));
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in only print modified registers Trace simulator debug messages Implied by trace sim abort randomize hashes to avoid predictable hash Fixed seed to use to hash property Print the time it takes to deserialize the snapshot A filename with extra code to be included in the A file to write the raw snapshot bytes to(mksnapshot only)") DEFINE_STRING(raw_context_file
enable harmony numeric enable harmony object literal extensions Optimize object size
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define JITHEADER_VERSION
#define CHECK_NE(unexpected, value)
#define DCHECK(condition)
int SNPrintF(Vector< char > str, const char *format,...)
Debugger support for the V8 JavaScript engine.
static FILE * FOpen(const char *path, const char *mode)