V8 Project
assembler-x64.cc
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1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #include "src/v8.h"
6 
7 #if V8_TARGET_ARCH_X64
8 
9 #include "src/base/bits.h"
10 #include "src/macro-assembler.h"
11 #include "src/serialize.h"
12 
13 namespace v8 {
14 namespace internal {
15 
16 // -----------------------------------------------------------------------------
17 // Implementation of CpuFeatures
18 
19 void CpuFeatures::ProbeImpl(bool cross_compile) {
20  base::CPU cpu;
21  CHECK(cpu.has_sse2()); // SSE2 support is mandatory.
22  CHECK(cpu.has_cmov()); // CMOV support is mandatory.
23 
24  // Only use statically determined features for cross compile (snapshot).
25  if (cross_compile) return;
26 
27  if (cpu.has_sse41() && FLAG_enable_sse4_1) supported_ |= 1u << SSE4_1;
28  if (cpu.has_sse3() && FLAG_enable_sse3) supported_ |= 1u << SSE3;
29  // SAHF is not generally available in long mode.
30  if (cpu.has_sahf() && FLAG_enable_sahf) supported_|= 1u << SAHF;
31 }
32 
33 
34 void CpuFeatures::PrintTarget() { }
36 
37 
38 // -----------------------------------------------------------------------------
39 // Implementation of RelocInfo
40 
41 // Patch the code at the current PC with a call to the target address.
42 // Additional guard int3 instructions can be added if required.
43 void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) {
44  int code_size = Assembler::kCallSequenceLength + guard_bytes;
45 
46  // Create a code patcher.
47  CodePatcher patcher(pc_, code_size);
48 
49  // Add a label for checking the size of the code used for returning.
50 #ifdef DEBUG
51  Label check_codesize;
52  patcher.masm()->bind(&check_codesize);
53 #endif
54 
55  // Patch the code.
56  patcher.masm()->movp(kScratchRegister, reinterpret_cast<void*>(target),
58  patcher.masm()->call(kScratchRegister);
59 
60  // Check that the size of the code generated is as expected.
62  patcher.masm()->SizeOfCodeGeneratedSince(&check_codesize));
63 
64  // Add the requested number of int3 instructions after the call.
65  for (int i = 0; i < guard_bytes; i++) {
66  patcher.masm()->int3();
67  }
68 }
69 
70 
71 void RelocInfo::PatchCode(byte* instructions, int instruction_count) {
72  // Patch the code at the current address with the supplied instructions.
73  for (int i = 0; i < instruction_count; i++) {
74  *(pc_ + i) = *(instructions + i);
75  }
76 
77  // Indicate that code has changed.
78  CpuFeatures::FlushICache(pc_, instruction_count);
79 }
80 
81 
82 // -----------------------------------------------------------------------------
83 // Register constants.
84 
85 const int
86  Register::kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters] = {
87  // rax, rbx, rdx, rcx, rsi, rdi, r8, r9, r11, r14, r15
88  0, 3, 2, 1, 6, 7, 8, 9, 11, 14, 15
89 };
90 
92  0, 3, 2, 1, -1, -1, 4, 5, 6, 7, -1, 8, -1, -1, 9, 10
93 };
94 
95 
96 // -----------------------------------------------------------------------------
97 // Implementation of Operand
98 
99 Operand::Operand(Register base, int32_t disp) : rex_(0) {
100  len_ = 1;
101  if (base.is(rsp) || base.is(r12)) {
102  // SIB byte is needed to encode (rsp + offset) or (r12 + offset).
103  set_sib(times_1, rsp, base);
104  }
105 
106  if (disp == 0 && !base.is(rbp) && !base.is(r13)) {
107  set_modrm(0, base);
108  } else if (is_int8(disp)) {
109  set_modrm(1, base);
110  set_disp8(disp);
111  } else {
112  set_modrm(2, base);
113  set_disp32(disp);
114  }
115 }
116 
117 
118 Operand::Operand(Register base,
119  Register index,
120  ScaleFactor scale,
121  int32_t disp) : rex_(0) {
122  DCHECK(!index.is(rsp));
123  len_ = 1;
124  set_sib(scale, index, base);
125  if (disp == 0 && !base.is(rbp) && !base.is(r13)) {
126  // This call to set_modrm doesn't overwrite the REX.B (or REX.X) bits
127  // possibly set by set_sib.
128  set_modrm(0, rsp);
129  } else if (is_int8(disp)) {
130  set_modrm(1, rsp);
131  set_disp8(disp);
132  } else {
133  set_modrm(2, rsp);
134  set_disp32(disp);
135  }
136 }
137 
138 
139 Operand::Operand(Register index,
140  ScaleFactor scale,
141  int32_t disp) : rex_(0) {
142  DCHECK(!index.is(rsp));
143  len_ = 1;
144  set_modrm(0, rsp);
145  set_sib(scale, index, rbp);
146  set_disp32(disp);
147 }
148 
149 
150 Operand::Operand(const Operand& operand, int32_t offset) {
151  DCHECK(operand.len_ >= 1);
152  // Operand encodes REX ModR/M [SIB] [Disp].
153  byte modrm = operand.buf_[0];
154  DCHECK(modrm < 0xC0); // Disallow mode 3 (register target).
155  bool has_sib = ((modrm & 0x07) == 0x04);
156  byte mode = modrm & 0xC0;
157  int disp_offset = has_sib ? 2 : 1;
158  int base_reg = (has_sib ? operand.buf_[1] : modrm) & 0x07;
159  // Mode 0 with rbp/r13 as ModR/M or SIB base register always has a 32-bit
160  // displacement.
161  bool is_baseless = (mode == 0) && (base_reg == 0x05); // No base or RIP base.
162  int32_t disp_value = 0;
163  if (mode == 0x80 || is_baseless) {
164  // Mode 2 or mode 0 with rbp/r13 as base: Word displacement.
165  disp_value = *bit_cast<const int32_t*>(&operand.buf_[disp_offset]);
166  } else if (mode == 0x40) {
167  // Mode 1: Byte displacement.
168  disp_value = static_cast<signed char>(operand.buf_[disp_offset]);
169  }
170 
171  // Write new operand with same registers, but with modified displacement.
172  DCHECK(offset >= 0 ? disp_value + offset > disp_value
173  : disp_value + offset < disp_value); // No overflow.
174  disp_value += offset;
175  rex_ = operand.rex_;
176  if (!is_int8(disp_value) || is_baseless) {
177  // Need 32 bits of displacement, mode 2 or mode 1 with register rbp/r13.
178  buf_[0] = (modrm & 0x3f) | (is_baseless ? 0x00 : 0x80);
179  len_ = disp_offset + 4;
180  Memory::int32_at(&buf_[disp_offset]) = disp_value;
181  } else if (disp_value != 0 || (base_reg == 0x05)) {
182  // Need 8 bits of displacement.
183  buf_[0] = (modrm & 0x3f) | 0x40; // Mode 1.
184  len_ = disp_offset + 1;
185  buf_[disp_offset] = static_cast<byte>(disp_value);
186  } else {
187  // Need no displacement.
188  buf_[0] = (modrm & 0x3f); // Mode 0.
189  len_ = disp_offset;
190  }
191  if (has_sib) {
192  buf_[1] = operand.buf_[1];
193  }
194 }
195 
196 
197 bool Operand::AddressUsesRegister(Register reg) const {
198  int code = reg.code();
199  DCHECK((buf_[0] & 0xC0) != 0xC0); // Always a memory operand.
200  // Start with only low three bits of base register. Initial decoding doesn't
201  // distinguish on the REX.B bit.
202  int base_code = buf_[0] & 0x07;
203  if (base_code == rsp.code()) {
204  // SIB byte present in buf_[1].
205  // Check the index register from the SIB byte + REX.X prefix.
206  int index_code = ((buf_[1] >> 3) & 0x07) | ((rex_ & 0x02) << 2);
207  // Index code (including REX.X) of 0x04 (rsp) means no index register.
208  if (index_code != rsp.code() && index_code == code) return true;
209  // Add REX.B to get the full base register code.
210  base_code = (buf_[1] & 0x07) | ((rex_ & 0x01) << 3);
211  // A base register of 0x05 (rbp) with mod = 0 means no base register.
212  if (base_code == rbp.code() && ((buf_[0] & 0xC0) == 0)) return false;
213  return code == base_code;
214  } else {
215  // A base register with low bits of 0x05 (rbp or r13) and mod = 0 means
216  // no base register.
217  if (base_code == rbp.code() && ((buf_[0] & 0xC0) == 0)) return false;
218  base_code |= ((rex_ & 0x01) << 3);
219  return code == base_code;
220  }
221 }
222 
223 
224 // -----------------------------------------------------------------------------
225 // Implementation of Assembler.
226 
227 #ifdef GENERATED_CODE_COVERAGE
228 static void InitCoverageLog();
229 #endif
230 
231 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size)
232  : AssemblerBase(isolate, buffer, buffer_size),
233  code_targets_(100),
234  positions_recorder_(this) {
235  // Clear the buffer in debug mode unless it was provided by the
236  // caller in which case we can't be sure it's okay to overwrite
237  // existing code in it.
238 #ifdef DEBUG
239  if (own_buffer_) {
240  memset(buffer_, 0xCC, buffer_size_); // int3
241  }
242 #endif
243 
244  reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_);
245 
246 
247 #ifdef GENERATED_CODE_COVERAGE
248  InitCoverageLog();
249 #endif
250 }
251 
252 
253 void Assembler::GetCode(CodeDesc* desc) {
254  // Finalize code (at this point overflow() may be true, but the gap ensures
255  // that we are still not overlapping instructions and relocation info).
256  DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
257  // Set up code descriptor.
258  desc->buffer = buffer_;
259  desc->buffer_size = buffer_size_;
260  desc->instr_size = pc_offset();
261  DCHECK(desc->instr_size > 0); // Zero-size code objects upset the system.
262  desc->reloc_size =
263  static_cast<int>((buffer_ + buffer_size_) - reloc_info_writer.pos());
264  desc->origin = this;
265 }
266 
267 
268 void Assembler::Align(int m) {
270  int delta = (m - (pc_offset() & (m - 1))) & (m - 1);
271  Nop(delta);
272 }
273 
274 
275 void Assembler::CodeTargetAlign() {
276  Align(16); // Preferred alignment of jump targets on x64.
277 }
278 
279 
280 bool Assembler::IsNop(Address addr) {
281  Address a = addr;
282  while (*a == 0x66) a++;
283  if (*a == 0x90) return true;
284  if (a[0] == 0xf && a[1] == 0x1f) return true;
285  return false;
286 }
287 
288 
289 void Assembler::bind_to(Label* L, int pos) {
290  DCHECK(!L->is_bound()); // Label may only be bound once.
291  DCHECK(0 <= pos && pos <= pc_offset()); // Position must be valid.
292  if (L->is_linked()) {
293  int current = L->pos();
294  int next = long_at(current);
295  while (next != current) {
296  // Relative address, relative to point after address.
297  int imm32 = pos - (current + sizeof(int32_t));
298  long_at_put(current, imm32);
299  current = next;
300  next = long_at(next);
301  }
302  // Fix up last fixup on linked list.
303  int last_imm32 = pos - (current + sizeof(int32_t));
304  long_at_put(current, last_imm32);
305  }
306  while (L->is_near_linked()) {
307  int fixup_pos = L->near_link_pos();
308  int offset_to_next =
309  static_cast<int>(*reinterpret_cast<int8_t*>(addr_at(fixup_pos)));
310  DCHECK(offset_to_next <= 0);
311  int disp = pos - (fixup_pos + sizeof(int8_t));
312  CHECK(is_int8(disp));
313  set_byte_at(fixup_pos, disp);
314  if (offset_to_next < 0) {
315  L->link_to(fixup_pos + offset_to_next, Label::kNear);
316  } else {
317  L->UnuseNear();
318  }
319  }
320  L->bind_to(pos);
321 }
322 
323 
324 void Assembler::bind(Label* L) {
325  bind_to(L, pc_offset());
326 }
327 
328 
329 void Assembler::GrowBuffer() {
330  DCHECK(buffer_overflow());
331  if (!own_buffer_) FATAL("external code buffer is too small");
332 
333  // Compute new buffer size.
334  CodeDesc desc; // the new buffer
335  desc.buffer_size = 2 * buffer_size_;
336 
337  // Some internal data structures overflow for very large buffers,
338  // they must ensure that kMaximalBufferSize is not too large.
339  if ((desc.buffer_size > kMaximalBufferSize) ||
340  (desc.buffer_size > isolate()->heap()->MaxOldGenerationSize())) {
341  V8::FatalProcessOutOfMemory("Assembler::GrowBuffer");
342  }
343 
344  // Set up new buffer.
345  desc.buffer = NewArray<byte>(desc.buffer_size);
346  desc.instr_size = pc_offset();
347  desc.reloc_size =
348  static_cast<int>((buffer_ + buffer_size_) - (reloc_info_writer.pos()));
349 
350  // Clear the buffer in debug mode. Use 'int3' instructions to make
351  // sure to get into problems if we ever run uninitialized code.
352 #ifdef DEBUG
353  memset(desc.buffer, 0xCC, desc.buffer_size);
354 #endif
355 
356  // Copy the data.
357  intptr_t pc_delta = desc.buffer - buffer_;
358  intptr_t rc_delta = (desc.buffer + desc.buffer_size) -
359  (buffer_ + buffer_size_);
360  MemMove(desc.buffer, buffer_, desc.instr_size);
361  MemMove(rc_delta + reloc_info_writer.pos(), reloc_info_writer.pos(),
362  desc.reloc_size);
363 
364  // Switch buffers.
365  DeleteArray(buffer_);
366  buffer_ = desc.buffer;
367  buffer_size_ = desc.buffer_size;
368  pc_ += pc_delta;
369  reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta,
370  reloc_info_writer.last_pc() + pc_delta);
371 
372  // Relocate runtime entries.
373  for (RelocIterator it(desc); !it.done(); it.next()) {
374  RelocInfo::Mode rmode = it.rinfo()->rmode();
375  if (rmode == RelocInfo::INTERNAL_REFERENCE) {
376  intptr_t* p = reinterpret_cast<intptr_t*>(it.rinfo()->pc());
377  if (*p != 0) { // 0 means uninitialized.
378  *p += pc_delta;
379  }
380  }
381  }
382 
383  DCHECK(!buffer_overflow());
384 }
385 
386 
387 void Assembler::emit_operand(int code, const Operand& adr) {
388  DCHECK(is_uint3(code));
389  const unsigned length = adr.len_;
390  DCHECK(length > 0);
391 
392  // Emit updated ModR/M byte containing the given register.
393  DCHECK((adr.buf_[0] & 0x38) == 0);
394  pc_[0] = adr.buf_[0] | code << 3;
395 
396  // Emit the rest of the encoded operand.
397  for (unsigned i = 1; i < length; i++) pc_[i] = adr.buf_[i];
398  pc_ += length;
399 }
400 
401 
402 // Assembler Instruction implementations.
403 
404 void Assembler::arithmetic_op(byte opcode,
405  Register reg,
406  const Operand& op,
407  int size) {
408  EnsureSpace ensure_space(this);
409  emit_rex(reg, op, size);
410  emit(opcode);
411  emit_operand(reg, op);
412 }
413 
414 
415 void Assembler::arithmetic_op(byte opcode,
416  Register reg,
417  Register rm_reg,
418  int size) {
419  EnsureSpace ensure_space(this);
420  DCHECK((opcode & 0xC6) == 2);
421  if (rm_reg.low_bits() == 4) { // Forces SIB byte.
422  // Swap reg and rm_reg and change opcode operand order.
423  emit_rex(rm_reg, reg, size);
424  emit(opcode ^ 0x02);
425  emit_modrm(rm_reg, reg);
426  } else {
427  emit_rex(reg, rm_reg, size);
428  emit(opcode);
429  emit_modrm(reg, rm_reg);
430  }
431 }
432 
433 
434 void Assembler::arithmetic_op_16(byte opcode, Register reg, Register rm_reg) {
435  EnsureSpace ensure_space(this);
436  DCHECK((opcode & 0xC6) == 2);
437  if (rm_reg.low_bits() == 4) { // Forces SIB byte.
438  // Swap reg and rm_reg and change opcode operand order.
439  emit(0x66);
440  emit_optional_rex_32(rm_reg, reg);
441  emit(opcode ^ 0x02);
442  emit_modrm(rm_reg, reg);
443  } else {
444  emit(0x66);
445  emit_optional_rex_32(reg, rm_reg);
446  emit(opcode);
447  emit_modrm(reg, rm_reg);
448  }
449 }
450 
451 
452 void Assembler::arithmetic_op_16(byte opcode,
453  Register reg,
454  const Operand& rm_reg) {
455  EnsureSpace ensure_space(this);
456  emit(0x66);
457  emit_optional_rex_32(reg, rm_reg);
458  emit(opcode);
459  emit_operand(reg, rm_reg);
460 }
461 
462 
463 void Assembler::arithmetic_op_8(byte opcode, Register reg, const Operand& op) {
464  EnsureSpace ensure_space(this);
465  if (!reg.is_byte_register()) {
466  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
467  emit_rex_32(reg);
468  }
469  emit(opcode);
470  emit_operand(reg, op);
471 }
472 
473 
474 void Assembler::arithmetic_op_8(byte opcode, Register reg, Register rm_reg) {
475  EnsureSpace ensure_space(this);
476  DCHECK((opcode & 0xC6) == 2);
477  if (rm_reg.low_bits() == 4) { // Forces SIB byte.
478  // Swap reg and rm_reg and change opcode operand order.
479  if (!rm_reg.is_byte_register() || !reg.is_byte_register()) {
480  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
481  emit_rex_32(rm_reg, reg);
482  }
483  emit(opcode ^ 0x02);
484  emit_modrm(rm_reg, reg);
485  } else {
486  if (!reg.is_byte_register() || !rm_reg.is_byte_register()) {
487  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
488  emit_rex_32(reg, rm_reg);
489  }
490  emit(opcode);
491  emit_modrm(reg, rm_reg);
492  }
493 }
494 
495 
496 void Assembler::immediate_arithmetic_op(byte subcode,
497  Register dst,
498  Immediate src,
499  int size) {
500  EnsureSpace ensure_space(this);
501  emit_rex(dst, size);
502  if (is_int8(src.value_)) {
503  emit(0x83);
504  emit_modrm(subcode, dst);
505  emit(src.value_);
506  } else if (dst.is(rax)) {
507  emit(0x05 | (subcode << 3));
508  emitl(src.value_);
509  } else {
510  emit(0x81);
511  emit_modrm(subcode, dst);
512  emitl(src.value_);
513  }
514 }
515 
516 void Assembler::immediate_arithmetic_op(byte subcode,
517  const Operand& dst,
518  Immediate src,
519  int size) {
520  EnsureSpace ensure_space(this);
521  emit_rex(dst, size);
522  if (is_int8(src.value_)) {
523  emit(0x83);
524  emit_operand(subcode, dst);
525  emit(src.value_);
526  } else {
527  emit(0x81);
528  emit_operand(subcode, dst);
529  emitl(src.value_);
530  }
531 }
532 
533 
534 void Assembler::immediate_arithmetic_op_16(byte subcode,
535  Register dst,
536  Immediate src) {
537  EnsureSpace ensure_space(this);
538  emit(0x66); // Operand size override prefix.
539  emit_optional_rex_32(dst);
540  if (is_int8(src.value_)) {
541  emit(0x83);
542  emit_modrm(subcode, dst);
543  emit(src.value_);
544  } else if (dst.is(rax)) {
545  emit(0x05 | (subcode << 3));
546  emitw(src.value_);
547  } else {
548  emit(0x81);
549  emit_modrm(subcode, dst);
550  emitw(src.value_);
551  }
552 }
553 
554 
555 void Assembler::immediate_arithmetic_op_16(byte subcode,
556  const Operand& dst,
557  Immediate src) {
558  EnsureSpace ensure_space(this);
559  emit(0x66); // Operand size override prefix.
560  emit_optional_rex_32(dst);
561  if (is_int8(src.value_)) {
562  emit(0x83);
563  emit_operand(subcode, dst);
564  emit(src.value_);
565  } else {
566  emit(0x81);
567  emit_operand(subcode, dst);
568  emitw(src.value_);
569  }
570 }
571 
572 
573 void Assembler::immediate_arithmetic_op_8(byte subcode,
574  const Operand& dst,
575  Immediate src) {
576  EnsureSpace ensure_space(this);
577  emit_optional_rex_32(dst);
578  DCHECK(is_int8(src.value_) || is_uint8(src.value_));
579  emit(0x80);
580  emit_operand(subcode, dst);
581  emit(src.value_);
582 }
583 
584 
585 void Assembler::immediate_arithmetic_op_8(byte subcode,
586  Register dst,
587  Immediate src) {
588  EnsureSpace ensure_space(this);
589  if (!dst.is_byte_register()) {
590  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
591  emit_rex_32(dst);
592  }
593  DCHECK(is_int8(src.value_) || is_uint8(src.value_));
594  emit(0x80);
595  emit_modrm(subcode, dst);
596  emit(src.value_);
597 }
598 
599 
600 void Assembler::shift(Register dst,
601  Immediate shift_amount,
602  int subcode,
603  int size) {
604  EnsureSpace ensure_space(this);
605  DCHECK(size == kInt64Size ? is_uint6(shift_amount.value_)
606  : is_uint5(shift_amount.value_));
607  if (shift_amount.value_ == 1) {
608  emit_rex(dst, size);
609  emit(0xD1);
610  emit_modrm(subcode, dst);
611  } else {
612  emit_rex(dst, size);
613  emit(0xC1);
614  emit_modrm(subcode, dst);
615  emit(shift_amount.value_);
616  }
617 }
618 
619 
620 void Assembler::shift(Register dst, int subcode, int size) {
621  EnsureSpace ensure_space(this);
622  emit_rex(dst, size);
623  emit(0xD3);
624  emit_modrm(subcode, dst);
625 }
626 
627 
628 void Assembler::bt(const Operand& dst, Register src) {
629  EnsureSpace ensure_space(this);
630  emit_rex_64(src, dst);
631  emit(0x0F);
632  emit(0xA3);
633  emit_operand(src, dst);
634 }
635 
636 
637 void Assembler::bts(const Operand& dst, Register src) {
638  EnsureSpace ensure_space(this);
639  emit_rex_64(src, dst);
640  emit(0x0F);
641  emit(0xAB);
642  emit_operand(src, dst);
643 }
644 
645 
646 void Assembler::bsrl(Register dst, Register src) {
647  EnsureSpace ensure_space(this);
648  emit_optional_rex_32(dst, src);
649  emit(0x0F);
650  emit(0xBD);
651  emit_modrm(dst, src);
652 }
653 
654 
655 void Assembler::call(Label* L) {
656  positions_recorder()->WriteRecordedPositions();
657  EnsureSpace ensure_space(this);
658  // 1110 1000 #32-bit disp.
659  emit(0xE8);
660  if (L->is_bound()) {
661  int offset = L->pos() - pc_offset() - sizeof(int32_t);
662  DCHECK(offset <= 0);
663  emitl(offset);
664  } else if (L->is_linked()) {
665  emitl(L->pos());
666  L->link_to(pc_offset() - sizeof(int32_t));
667  } else {
668  DCHECK(L->is_unused());
669  int32_t current = pc_offset();
670  emitl(current);
671  L->link_to(current);
672  }
673 }
674 
675 
676 void Assembler::call(Address entry, RelocInfo::Mode rmode) {
677  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
678  positions_recorder()->WriteRecordedPositions();
679  EnsureSpace ensure_space(this);
680  // 1110 1000 #32-bit disp.
681  emit(0xE8);
682  emit_runtime_entry(entry, rmode);
683 }
684 
685 
686 void Assembler::call(Handle<Code> target,
687  RelocInfo::Mode rmode,
688  TypeFeedbackId ast_id) {
689  positions_recorder()->WriteRecordedPositions();
690  EnsureSpace ensure_space(this);
691  // 1110 1000 #32-bit disp.
692  emit(0xE8);
693  emit_code_target(target, rmode, ast_id);
694 }
695 
696 
697 void Assembler::call(Register adr) {
698  positions_recorder()->WriteRecordedPositions();
699  EnsureSpace ensure_space(this);
700  // Opcode: FF /2 r64.
701  emit_optional_rex_32(adr);
702  emit(0xFF);
703  emit_modrm(0x2, adr);
704 }
705 
706 
707 void Assembler::call(const Operand& op) {
708  positions_recorder()->WriteRecordedPositions();
709  EnsureSpace ensure_space(this);
710  // Opcode: FF /2 m64.
711  emit_optional_rex_32(op);
712  emit(0xFF);
713  emit_operand(0x2, op);
714 }
715 
716 
717 // Calls directly to the given address using a relative offset.
718 // Should only ever be used in Code objects for calls within the
719 // same Code object. Should not be used when generating new code (use labels),
720 // but only when patching existing code.
721 void Assembler::call(Address target) {
722  positions_recorder()->WriteRecordedPositions();
723  EnsureSpace ensure_space(this);
724  // 1110 1000 #32-bit disp.
725  emit(0xE8);
726  Address source = pc_ + 4;
727  intptr_t displacement = target - source;
728  DCHECK(is_int32(displacement));
729  emitl(static_cast<int32_t>(displacement));
730 }
731 
732 
733 void Assembler::clc() {
734  EnsureSpace ensure_space(this);
735  emit(0xF8);
736 }
737 
738 
739 void Assembler::cld() {
740  EnsureSpace ensure_space(this);
741  emit(0xFC);
742 }
743 
744 
745 void Assembler::cdq() {
746  EnsureSpace ensure_space(this);
747  emit(0x99);
748 }
749 
750 
751 void Assembler::cmovq(Condition cc, Register dst, Register src) {
752  if (cc == always) {
753  movq(dst, src);
754  } else if (cc == never) {
755  return;
756  }
757  // No need to check CpuInfo for CMOV support, it's a required part of the
758  // 64-bit architecture.
759  DCHECK(cc >= 0); // Use mov for unconditional moves.
760  EnsureSpace ensure_space(this);
761  // Opcode: REX.W 0f 40 + cc /r.
762  emit_rex_64(dst, src);
763  emit(0x0f);
764  emit(0x40 + cc);
765  emit_modrm(dst, src);
766 }
767 
768 
769 void Assembler::cmovq(Condition cc, Register dst, const Operand& src) {
770  if (cc == always) {
771  movq(dst, src);
772  } else if (cc == never) {
773  return;
774  }
775  DCHECK(cc >= 0);
776  EnsureSpace ensure_space(this);
777  // Opcode: REX.W 0f 40 + cc /r.
778  emit_rex_64(dst, src);
779  emit(0x0f);
780  emit(0x40 + cc);
781  emit_operand(dst, src);
782 }
783 
784 
785 void Assembler::cmovl(Condition cc, Register dst, Register src) {
786  if (cc == always) {
787  movl(dst, src);
788  } else if (cc == never) {
789  return;
790  }
791  DCHECK(cc >= 0);
792  EnsureSpace ensure_space(this);
793  // Opcode: 0f 40 + cc /r.
794  emit_optional_rex_32(dst, src);
795  emit(0x0f);
796  emit(0x40 + cc);
797  emit_modrm(dst, src);
798 }
799 
800 
801 void Assembler::cmovl(Condition cc, Register dst, const Operand& src) {
802  if (cc == always) {
803  movl(dst, src);
804  } else if (cc == never) {
805  return;
806  }
807  DCHECK(cc >= 0);
808  EnsureSpace ensure_space(this);
809  // Opcode: 0f 40 + cc /r.
810  emit_optional_rex_32(dst, src);
811  emit(0x0f);
812  emit(0x40 + cc);
813  emit_operand(dst, src);
814 }
815 
816 
817 void Assembler::cmpb_al(Immediate imm8) {
818  DCHECK(is_int8(imm8.value_) || is_uint8(imm8.value_));
819  EnsureSpace ensure_space(this);
820  emit(0x3c);
821  emit(imm8.value_);
822 }
823 
824 
825 void Assembler::cpuid() {
826  EnsureSpace ensure_space(this);
827  emit(0x0F);
828  emit(0xA2);
829 }
830 
831 
832 void Assembler::cqo() {
833  EnsureSpace ensure_space(this);
834  emit_rex_64();
835  emit(0x99);
836 }
837 
838 
839 void Assembler::emit_dec(Register dst, int size) {
840  EnsureSpace ensure_space(this);
841  emit_rex(dst, size);
842  emit(0xFF);
843  emit_modrm(0x1, dst);
844 }
845 
846 
847 void Assembler::emit_dec(const Operand& dst, int size) {
848  EnsureSpace ensure_space(this);
849  emit_rex(dst, size);
850  emit(0xFF);
851  emit_operand(1, dst);
852 }
853 
854 
855 void Assembler::decb(Register dst) {
856  EnsureSpace ensure_space(this);
857  if (!dst.is_byte_register()) {
858  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
859  emit_rex_32(dst);
860  }
861  emit(0xFE);
862  emit_modrm(0x1, dst);
863 }
864 
865 
866 void Assembler::decb(const Operand& dst) {
867  EnsureSpace ensure_space(this);
868  emit_optional_rex_32(dst);
869  emit(0xFE);
870  emit_operand(1, dst);
871 }
872 
873 
874 void Assembler::enter(Immediate size) {
875  EnsureSpace ensure_space(this);
876  emit(0xC8);
877  emitw(size.value_); // 16 bit operand, always.
878  emit(0);
879 }
880 
881 
882 void Assembler::hlt() {
883  EnsureSpace ensure_space(this);
884  emit(0xF4);
885 }
886 
887 
888 void Assembler::emit_idiv(Register src, int size) {
889  EnsureSpace ensure_space(this);
890  emit_rex(src, size);
891  emit(0xF7);
892  emit_modrm(0x7, src);
893 }
894 
895 
896 void Assembler::emit_div(Register src, int size) {
897  EnsureSpace ensure_space(this);
898  emit_rex(src, size);
899  emit(0xF7);
900  emit_modrm(0x6, src);
901 }
902 
903 
904 void Assembler::emit_imul(Register src, int size) {
905  EnsureSpace ensure_space(this);
906  emit_rex(src, size);
907  emit(0xF7);
908  emit_modrm(0x5, src);
909 }
910 
911 
912 void Assembler::emit_imul(Register dst, Register src, int size) {
913  EnsureSpace ensure_space(this);
914  emit_rex(dst, src, size);
915  emit(0x0F);
916  emit(0xAF);
917  emit_modrm(dst, src);
918 }
919 
920 
921 void Assembler::emit_imul(Register dst, const Operand& src, int size) {
922  EnsureSpace ensure_space(this);
923  emit_rex(dst, src, size);
924  emit(0x0F);
925  emit(0xAF);
926  emit_operand(dst, src);
927 }
928 
929 
930 void Assembler::emit_imul(Register dst, Register src, Immediate imm, int size) {
931  EnsureSpace ensure_space(this);
932  emit_rex(dst, src, size);
933  if (is_int8(imm.value_)) {
934  emit(0x6B);
935  emit_modrm(dst, src);
936  emit(imm.value_);
937  } else {
938  emit(0x69);
939  emit_modrm(dst, src);
940  emitl(imm.value_);
941  }
942 }
943 
944 
945 void Assembler::emit_imul(Register dst, const Operand& src, Immediate imm,
946  int size) {
947  EnsureSpace ensure_space(this);
948  emit_rex(dst, src, size);
949  if (is_int8(imm.value_)) {
950  emit(0x6B);
951  } else {
952  emit(0x69);
953  }
954  emit_operand(dst, src);
955  emit(imm.value_);
956 }
957 
958 
959 void Assembler::emit_inc(Register dst, int size) {
960  EnsureSpace ensure_space(this);
961  emit_rex(dst, size);
962  emit(0xFF);
963  emit_modrm(0x0, dst);
964 }
965 
966 
967 void Assembler::emit_inc(const Operand& dst, int size) {
968  EnsureSpace ensure_space(this);
969  emit_rex(dst, size);
970  emit(0xFF);
971  emit_operand(0, dst);
972 }
973 
974 
975 void Assembler::int3() {
976  EnsureSpace ensure_space(this);
977  emit(0xCC);
978 }
979 
980 
981 void Assembler::j(Condition cc, Label* L, Label::Distance distance) {
982  if (cc == always) {
983  jmp(L);
984  return;
985  } else if (cc == never) {
986  return;
987  }
988  EnsureSpace ensure_space(this);
989  DCHECK(is_uint4(cc));
990  if (L->is_bound()) {
991  const int short_size = 2;
992  const int long_size = 6;
993  int offs = L->pos() - pc_offset();
994  DCHECK(offs <= 0);
995  // Determine whether we can use 1-byte offsets for backwards branches,
996  // which have a max range of 128 bytes.
997 
998  // We also need to check predictable_code_size() flag here, because on x64,
999  // when the full code generator recompiles code for debugging, some places
1000  // need to be padded out to a certain size. The debugger is keeping track of
1001  // how often it did this so that it can adjust return addresses on the
1002  // stack, but if the size of jump instructions can also change, that's not
1003  // enough and the calculated offsets would be incorrect.
1004  if (is_int8(offs - short_size) && !predictable_code_size()) {
1005  // 0111 tttn #8-bit disp.
1006  emit(0x70 | cc);
1007  emit((offs - short_size) & 0xFF);
1008  } else {
1009  // 0000 1111 1000 tttn #32-bit disp.
1010  emit(0x0F);
1011  emit(0x80 | cc);
1012  emitl(offs - long_size);
1013  }
1014  } else if (distance == Label::kNear) {
1015  // 0111 tttn #8-bit disp
1016  emit(0x70 | cc);
1017  byte disp = 0x00;
1018  if (L->is_near_linked()) {
1019  int offset = L->near_link_pos() - pc_offset();
1020  DCHECK(is_int8(offset));
1021  disp = static_cast<byte>(offset & 0xFF);
1022  }
1023  L->link_to(pc_offset(), Label::kNear);
1024  emit(disp);
1025  } else if (L->is_linked()) {
1026  // 0000 1111 1000 tttn #32-bit disp.
1027  emit(0x0F);
1028  emit(0x80 | cc);
1029  emitl(L->pos());
1030  L->link_to(pc_offset() - sizeof(int32_t));
1031  } else {
1032  DCHECK(L->is_unused());
1033  emit(0x0F);
1034  emit(0x80 | cc);
1035  int32_t current = pc_offset();
1036  emitl(current);
1037  L->link_to(current);
1038  }
1039 }
1040 
1041 
1042 void Assembler::j(Condition cc, Address entry, RelocInfo::Mode rmode) {
1043  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
1044  EnsureSpace ensure_space(this);
1045  DCHECK(is_uint4(cc));
1046  emit(0x0F);
1047  emit(0x80 | cc);
1048  emit_runtime_entry(entry, rmode);
1049 }
1050 
1051 
1052 void Assembler::j(Condition cc,
1053  Handle<Code> target,
1054  RelocInfo::Mode rmode) {
1055  EnsureSpace ensure_space(this);
1056  DCHECK(is_uint4(cc));
1057  // 0000 1111 1000 tttn #32-bit disp.
1058  emit(0x0F);
1059  emit(0x80 | cc);
1060  emit_code_target(target, rmode);
1061 }
1062 
1063 
1064 void Assembler::jmp(Label* L, Label::Distance distance) {
1065  EnsureSpace ensure_space(this);
1066  const int short_size = sizeof(int8_t);
1067  const int long_size = sizeof(int32_t);
1068  if (L->is_bound()) {
1069  int offs = L->pos() - pc_offset() - 1;
1070  DCHECK(offs <= 0);
1071  if (is_int8(offs - short_size) && !predictable_code_size()) {
1072  // 1110 1011 #8-bit disp.
1073  emit(0xEB);
1074  emit((offs - short_size) & 0xFF);
1075  } else {
1076  // 1110 1001 #32-bit disp.
1077  emit(0xE9);
1078  emitl(offs - long_size);
1079  }
1080  } else if (distance == Label::kNear) {
1081  emit(0xEB);
1082  byte disp = 0x00;
1083  if (L->is_near_linked()) {
1084  int offset = L->near_link_pos() - pc_offset();
1085  DCHECK(is_int8(offset));
1086  disp = static_cast<byte>(offset & 0xFF);
1087  }
1088  L->link_to(pc_offset(), Label::kNear);
1089  emit(disp);
1090  } else if (L->is_linked()) {
1091  // 1110 1001 #32-bit disp.
1092  emit(0xE9);
1093  emitl(L->pos());
1094  L->link_to(pc_offset() - long_size);
1095  } else {
1096  // 1110 1001 #32-bit disp.
1097  DCHECK(L->is_unused());
1098  emit(0xE9);
1099  int32_t current = pc_offset();
1100  emitl(current);
1101  L->link_to(current);
1102  }
1103 }
1104 
1105 
1106 void Assembler::jmp(Handle<Code> target, RelocInfo::Mode rmode) {
1107  EnsureSpace ensure_space(this);
1108  // 1110 1001 #32-bit disp.
1109  emit(0xE9);
1110  emit_code_target(target, rmode);
1111 }
1112 
1113 
1114 void Assembler::jmp(Address entry, RelocInfo::Mode rmode) {
1115  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
1116  EnsureSpace ensure_space(this);
1117  DCHECK(RelocInfo::IsRuntimeEntry(rmode));
1118  emit(0xE9);
1119  emit_runtime_entry(entry, rmode);
1120 }
1121 
1122 
1123 void Assembler::jmp(Register target) {
1124  EnsureSpace ensure_space(this);
1125  // Opcode FF/4 r64.
1126  emit_optional_rex_32(target);
1127  emit(0xFF);
1128  emit_modrm(0x4, target);
1129 }
1130 
1131 
1132 void Assembler::jmp(const Operand& src) {
1133  EnsureSpace ensure_space(this);
1134  // Opcode FF/4 m64.
1135  emit_optional_rex_32(src);
1136  emit(0xFF);
1137  emit_operand(0x4, src);
1138 }
1139 
1140 
1141 void Assembler::emit_lea(Register dst, const Operand& src, int size) {
1142  EnsureSpace ensure_space(this);
1143  emit_rex(dst, src, size);
1144  emit(0x8D);
1145  emit_operand(dst, src);
1146 }
1147 
1148 
1149 void Assembler::load_rax(void* value, RelocInfo::Mode mode) {
1150  EnsureSpace ensure_space(this);
1151  if (kPointerSize == kInt64Size) {
1152  emit(0x48); // REX.W
1153  emit(0xA1);
1154  emitp(value, mode);
1155  } else {
1157  emit(0xA1);
1158  emitp(value, mode);
1159  // In 64-bit mode, need to zero extend the operand to 8 bytes.
1160  // See 2.2.1.4 in Intel64 and IA32 Architectures Software
1161  // Developer's Manual Volume 2.
1162  emitl(0);
1163  }
1164 }
1165 
1166 
1167 void Assembler::load_rax(ExternalReference ref) {
1168  load_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE);
1169 }
1170 
1171 
1172 void Assembler::leave() {
1173  EnsureSpace ensure_space(this);
1174  emit(0xC9);
1175 }
1176 
1177 
1178 void Assembler::movb(Register dst, const Operand& src) {
1179  EnsureSpace ensure_space(this);
1180  if (!dst.is_byte_register()) {
1181  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1182  emit_rex_32(dst, src);
1183  } else {
1184  emit_optional_rex_32(dst, src);
1185  }
1186  emit(0x8A);
1187  emit_operand(dst, src);
1188 }
1189 
1190 
1191 void Assembler::movb(Register dst, Immediate imm) {
1192  EnsureSpace ensure_space(this);
1193  if (!dst.is_byte_register()) {
1194  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1195  emit_rex_32(dst);
1196  }
1197  emit(0xB0 + dst.low_bits());
1198  emit(imm.value_);
1199 }
1200 
1201 
1202 void Assembler::movb(const Operand& dst, Register src) {
1203  EnsureSpace ensure_space(this);
1204  if (!src.is_byte_register()) {
1205  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1206  emit_rex_32(src, dst);
1207  } else {
1208  emit_optional_rex_32(src, dst);
1209  }
1210  emit(0x88);
1211  emit_operand(src, dst);
1212 }
1213 
1214 
1215 void Assembler::movb(const Operand& dst, Immediate imm) {
1216  EnsureSpace ensure_space(this);
1217  emit_optional_rex_32(dst);
1218  emit(0xC6);
1219  emit_operand(0x0, dst);
1220  emit(static_cast<byte>(imm.value_));
1221 }
1222 
1223 
1224 void Assembler::movw(Register dst, const Operand& src) {
1225  EnsureSpace ensure_space(this);
1226  emit(0x66);
1227  emit_optional_rex_32(dst, src);
1228  emit(0x8B);
1229  emit_operand(dst, src);
1230 }
1231 
1232 
1233 void Assembler::movw(const Operand& dst, Register src) {
1234  EnsureSpace ensure_space(this);
1235  emit(0x66);
1236  emit_optional_rex_32(src, dst);
1237  emit(0x89);
1238  emit_operand(src, dst);
1239 }
1240 
1241 
1242 void Assembler::movw(const Operand& dst, Immediate imm) {
1243  EnsureSpace ensure_space(this);
1244  emit(0x66);
1245  emit_optional_rex_32(dst);
1246  emit(0xC7);
1247  emit_operand(0x0, dst);
1248  emit(static_cast<byte>(imm.value_ & 0xff));
1249  emit(static_cast<byte>(imm.value_ >> 8));
1250 }
1251 
1252 
1253 void Assembler::emit_mov(Register dst, const Operand& src, int size) {
1254  EnsureSpace ensure_space(this);
1255  emit_rex(dst, src, size);
1256  emit(0x8B);
1257  emit_operand(dst, src);
1258 }
1259 
1260 
1261 void Assembler::emit_mov(Register dst, Register src, int size) {
1262  EnsureSpace ensure_space(this);
1263  if (src.low_bits() == 4) {
1264  emit_rex(src, dst, size);
1265  emit(0x89);
1266  emit_modrm(src, dst);
1267  } else {
1268  emit_rex(dst, src, size);
1269  emit(0x8B);
1270  emit_modrm(dst, src);
1271  }
1272 }
1273 
1274 
1275 void Assembler::emit_mov(const Operand& dst, Register src, int size) {
1276  EnsureSpace ensure_space(this);
1277  emit_rex(src, dst, size);
1278  emit(0x89);
1279  emit_operand(src, dst);
1280 }
1281 
1282 
1283 void Assembler::emit_mov(Register dst, Immediate value, int size) {
1284  EnsureSpace ensure_space(this);
1285  emit_rex(dst, size);
1286  if (size == kInt64Size) {
1287  emit(0xC7);
1288  emit_modrm(0x0, dst);
1289  } else {
1290  DCHECK(size == kInt32Size);
1291  emit(0xB8 + dst.low_bits());
1292  }
1293  emit(value);
1294 }
1295 
1296 
1297 void Assembler::emit_mov(const Operand& dst, Immediate value, int size) {
1298  EnsureSpace ensure_space(this);
1299  emit_rex(dst, size);
1300  emit(0xC7);
1301  emit_operand(0x0, dst);
1302  emit(value);
1303 }
1304 
1305 
1306 void Assembler::movp(Register dst, void* value, RelocInfo::Mode rmode) {
1307  EnsureSpace ensure_space(this);
1308  emit_rex(dst, kPointerSize);
1309  emit(0xB8 | dst.low_bits());
1310  emitp(value, rmode);
1311 }
1312 
1313 
1314 void Assembler::movq(Register dst, int64_t value) {
1315  EnsureSpace ensure_space(this);
1316  emit_rex_64(dst);
1317  emit(0xB8 | dst.low_bits());
1318  emitq(value);
1319 }
1320 
1321 
1322 void Assembler::movq(Register dst, uint64_t value) {
1323  movq(dst, static_cast<int64_t>(value));
1324 }
1325 
1326 
1327 // Loads the ip-relative location of the src label into the target location
1328 // (as a 32-bit offset sign extended to 64-bit).
1329 void Assembler::movl(const Operand& dst, Label* src) {
1330  EnsureSpace ensure_space(this);
1331  emit_optional_rex_32(dst);
1332  emit(0xC7);
1333  emit_operand(0, dst);
1334  if (src->is_bound()) {
1335  int offset = src->pos() - pc_offset() - sizeof(int32_t);
1336  DCHECK(offset <= 0);
1337  emitl(offset);
1338  } else if (src->is_linked()) {
1339  emitl(src->pos());
1340  src->link_to(pc_offset() - sizeof(int32_t));
1341  } else {
1342  DCHECK(src->is_unused());
1343  int32_t current = pc_offset();
1344  emitl(current);
1345  src->link_to(current);
1346  }
1347 }
1348 
1349 
1350 void Assembler::movsxbl(Register dst, const Operand& src) {
1351  EnsureSpace ensure_space(this);
1352  emit_optional_rex_32(dst, src);
1353  emit(0x0F);
1354  emit(0xBE);
1355  emit_operand(dst, src);
1356 }
1357 
1358 
1359 void Assembler::movsxbq(Register dst, const Operand& src) {
1360  EnsureSpace ensure_space(this);
1361  emit_rex_64(dst, src);
1362  emit(0x0F);
1363  emit(0xBE);
1364  emit_operand(dst, src);
1365 }
1366 
1367 
1368 void Assembler::movsxwl(Register dst, const Operand& src) {
1369  EnsureSpace ensure_space(this);
1370  emit_optional_rex_32(dst, src);
1371  emit(0x0F);
1372  emit(0xBF);
1373  emit_operand(dst, src);
1374 }
1375 
1376 
1377 void Assembler::movsxwq(Register dst, const Operand& src) {
1378  EnsureSpace ensure_space(this);
1379  emit_rex_64(dst, src);
1380  emit(0x0F);
1381  emit(0xBF);
1382  emit_operand(dst, src);
1383 }
1384 
1385 
1386 void Assembler::movsxlq(Register dst, Register src) {
1387  EnsureSpace ensure_space(this);
1388  emit_rex_64(dst, src);
1389  emit(0x63);
1390  emit_modrm(dst, src);
1391 }
1392 
1393 
1394 void Assembler::movsxlq(Register dst, const Operand& src) {
1395  EnsureSpace ensure_space(this);
1396  emit_rex_64(dst, src);
1397  emit(0x63);
1398  emit_operand(dst, src);
1399 }
1400 
1401 
1402 void Assembler::emit_movzxb(Register dst, const Operand& src, int size) {
1403  EnsureSpace ensure_space(this);
1404  // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1405  // there is no need to make this a 64 bit operation.
1406  emit_optional_rex_32(dst, src);
1407  emit(0x0F);
1408  emit(0xB6);
1409  emit_operand(dst, src);
1410 }
1411 
1412 
1413 void Assembler::emit_movzxb(Register dst, Register src, int size) {
1414  EnsureSpace ensure_space(this);
1415  // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1416  // there is no need to make this a 64 bit operation.
1417  if (!src.is_byte_register()) {
1418  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1419  emit_rex_32(dst, src);
1420  } else {
1421  emit_optional_rex_32(dst, src);
1422  }
1423  emit(0x0F);
1424  emit(0xB6);
1425  emit_modrm(dst, src);
1426 }
1427 
1428 
1429 void Assembler::emit_movzxw(Register dst, const Operand& src, int size) {
1430  EnsureSpace ensure_space(this);
1431  // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1432  // there is no need to make this a 64 bit operation.
1433  emit_optional_rex_32(dst, src);
1434  emit(0x0F);
1435  emit(0xB7);
1436  emit_operand(dst, src);
1437 }
1438 
1439 
1440 void Assembler::emit_movzxw(Register dst, Register src, int size) {
1441  EnsureSpace ensure_space(this);
1442  // 32 bit operations zero the top 32 bits of 64 bit registers. Therefore
1443  // there is no need to make this a 64 bit operation.
1444  emit_optional_rex_32(dst, src);
1445  emit(0x0F);
1446  emit(0xB7);
1447  emit_modrm(dst, src);
1448 }
1449 
1450 
1451 void Assembler::repmovsb() {
1452  EnsureSpace ensure_space(this);
1453  emit(0xF3);
1454  emit(0xA4);
1455 }
1456 
1457 
1458 void Assembler::repmovsw() {
1459  EnsureSpace ensure_space(this);
1460  emit(0x66); // Operand size override.
1461  emit(0xF3);
1462  emit(0xA4);
1463 }
1464 
1465 
1466 void Assembler::emit_repmovs(int size) {
1467  EnsureSpace ensure_space(this);
1468  emit(0xF3);
1469  emit_rex(size);
1470  emit(0xA5);
1471 }
1472 
1473 
1474 void Assembler::mul(Register src) {
1475  EnsureSpace ensure_space(this);
1476  emit_rex_64(src);
1477  emit(0xF7);
1478  emit_modrm(0x4, src);
1479 }
1480 
1481 
1482 void Assembler::emit_neg(Register dst, int size) {
1483  EnsureSpace ensure_space(this);
1484  emit_rex(dst, size);
1485  emit(0xF7);
1486  emit_modrm(0x3, dst);
1487 }
1488 
1489 
1490 void Assembler::emit_neg(const Operand& dst, int size) {
1491  EnsureSpace ensure_space(this);
1492  emit_rex_64(dst);
1493  emit(0xF7);
1494  emit_operand(3, dst);
1495 }
1496 
1497 
1498 void Assembler::nop() {
1499  EnsureSpace ensure_space(this);
1500  emit(0x90);
1501 }
1502 
1503 
1504 void Assembler::emit_not(Register dst, int size) {
1505  EnsureSpace ensure_space(this);
1506  emit_rex(dst, size);
1507  emit(0xF7);
1508  emit_modrm(0x2, dst);
1509 }
1510 
1511 
1512 void Assembler::emit_not(const Operand& dst, int size) {
1513  EnsureSpace ensure_space(this);
1514  emit_rex(dst, size);
1515  emit(0xF7);
1516  emit_operand(2, dst);
1517 }
1518 
1519 
1520 void Assembler::Nop(int n) {
1521  // The recommended muti-byte sequences of NOP instructions from the Intel 64
1522  // and IA-32 Architectures Software Developer's Manual.
1523  //
1524  // Length Assembly Byte Sequence
1525  // 2 bytes 66 NOP 66 90H
1526  // 3 bytes NOP DWORD ptr [EAX] 0F 1F 00H
1527  // 4 bytes NOP DWORD ptr [EAX + 00H] 0F 1F 40 00H
1528  // 5 bytes NOP DWORD ptr [EAX + EAX*1 + 00H] 0F 1F 44 00 00H
1529  // 6 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 00H] 66 0F 1F 44 00 00H
1530  // 7 bytes NOP DWORD ptr [EAX + 00000000H] 0F 1F 80 00 00 00 00H
1531  // 8 bytes NOP DWORD ptr [EAX + EAX*1 + 00000000H] 0F 1F 84 00 00 00 00 00H
1532  // 9 bytes 66 NOP DWORD ptr [EAX + EAX*1 + 66 0F 1F 84 00 00 00 00
1533  // 00000000H] 00H
1534 
1535  EnsureSpace ensure_space(this);
1536  while (n > 0) {
1537  switch (n) {
1538  case 2:
1539  emit(0x66);
1540  case 1:
1541  emit(0x90);
1542  return;
1543  case 3:
1544  emit(0x0f);
1545  emit(0x1f);
1546  emit(0x00);
1547  return;
1548  case 4:
1549  emit(0x0f);
1550  emit(0x1f);
1551  emit(0x40);
1552  emit(0x00);
1553  return;
1554  case 6:
1555  emit(0x66);
1556  case 5:
1557  emit(0x0f);
1558  emit(0x1f);
1559  emit(0x44);
1560  emit(0x00);
1561  emit(0x00);
1562  return;
1563  case 7:
1564  emit(0x0f);
1565  emit(0x1f);
1566  emit(0x80);
1567  emit(0x00);
1568  emit(0x00);
1569  emit(0x00);
1570  emit(0x00);
1571  return;
1572  default:
1573  case 11:
1574  emit(0x66);
1575  n--;
1576  case 10:
1577  emit(0x66);
1578  n--;
1579  case 9:
1580  emit(0x66);
1581  n--;
1582  case 8:
1583  emit(0x0f);
1584  emit(0x1f);
1585  emit(0x84);
1586  emit(0x00);
1587  emit(0x00);
1588  emit(0x00);
1589  emit(0x00);
1590  emit(0x00);
1591  n -= 8;
1592  }
1593  }
1594 }
1595 
1596 
1597 void Assembler::popq(Register dst) {
1598  EnsureSpace ensure_space(this);
1599  emit_optional_rex_32(dst);
1600  emit(0x58 | dst.low_bits());
1601 }
1602 
1603 
1604 void Assembler::popq(const Operand& dst) {
1605  EnsureSpace ensure_space(this);
1606  emit_optional_rex_32(dst);
1607  emit(0x8F);
1608  emit_operand(0, dst);
1609 }
1610 
1611 
1612 void Assembler::popfq() {
1613  EnsureSpace ensure_space(this);
1614  emit(0x9D);
1615 }
1616 
1617 
1618 void Assembler::pushq(Register src) {
1619  EnsureSpace ensure_space(this);
1620  emit_optional_rex_32(src);
1621  emit(0x50 | src.low_bits());
1622 }
1623 
1624 
1625 void Assembler::pushq(const Operand& src) {
1626  EnsureSpace ensure_space(this);
1627  emit_optional_rex_32(src);
1628  emit(0xFF);
1629  emit_operand(6, src);
1630 }
1631 
1632 
1633 void Assembler::pushq(Immediate value) {
1634  EnsureSpace ensure_space(this);
1635  if (is_int8(value.value_)) {
1636  emit(0x6A);
1637  emit(value.value_); // Emit low byte of value.
1638  } else {
1639  emit(0x68);
1640  emitl(value.value_);
1641  }
1642 }
1643 
1644 
1645 void Assembler::pushq_imm32(int32_t imm32) {
1646  EnsureSpace ensure_space(this);
1647  emit(0x68);
1648  emitl(imm32);
1649 }
1650 
1651 
1652 void Assembler::pushfq() {
1653  EnsureSpace ensure_space(this);
1654  emit(0x9C);
1655 }
1656 
1657 
1658 void Assembler::ret(int imm16) {
1659  EnsureSpace ensure_space(this);
1660  DCHECK(is_uint16(imm16));
1661  if (imm16 == 0) {
1662  emit(0xC3);
1663  } else {
1664  emit(0xC2);
1665  emit(imm16 & 0xFF);
1666  emit((imm16 >> 8) & 0xFF);
1667  }
1668 }
1669 
1670 
1671 void Assembler::setcc(Condition cc, Register reg) {
1672  if (cc > last_condition) {
1673  movb(reg, Immediate(cc == always ? 1 : 0));
1674  return;
1675  }
1676  EnsureSpace ensure_space(this);
1677  DCHECK(is_uint4(cc));
1678  if (!reg.is_byte_register()) {
1679  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1680  emit_rex_32(reg);
1681  }
1682  emit(0x0F);
1683  emit(0x90 | cc);
1684  emit_modrm(0x0, reg);
1685 }
1686 
1687 
1688 void Assembler::shld(Register dst, Register src) {
1689  EnsureSpace ensure_space(this);
1690  emit_rex_64(src, dst);
1691  emit(0x0F);
1692  emit(0xA5);
1693  emit_modrm(src, dst);
1694 }
1695 
1696 
1697 void Assembler::shrd(Register dst, Register src) {
1698  EnsureSpace ensure_space(this);
1699  emit_rex_64(src, dst);
1700  emit(0x0F);
1701  emit(0xAD);
1702  emit_modrm(src, dst);
1703 }
1704 
1705 
1706 void Assembler::emit_xchg(Register dst, Register src, int size) {
1707  EnsureSpace ensure_space(this);
1708  if (src.is(rax) || dst.is(rax)) { // Single-byte encoding
1709  Register other = src.is(rax) ? dst : src;
1710  emit_rex(other, size);
1711  emit(0x90 | other.low_bits());
1712  } else if (dst.low_bits() == 4) {
1713  emit_rex(dst, src, size);
1714  emit(0x87);
1715  emit_modrm(dst, src);
1716  } else {
1717  emit_rex(src, dst, size);
1718  emit(0x87);
1719  emit_modrm(src, dst);
1720  }
1721 }
1722 
1723 
1724 void Assembler::emit_xchg(Register dst, const Operand& src, int size) {
1725  EnsureSpace ensure_space(this);
1726  emit_rex(dst, src, size);
1727  emit(0x87);
1728  emit_operand(dst, src);
1729 }
1730 
1731 
1732 void Assembler::store_rax(void* dst, RelocInfo::Mode mode) {
1733  EnsureSpace ensure_space(this);
1734  if (kPointerSize == kInt64Size) {
1735  emit(0x48); // REX.W
1736  emit(0xA3);
1737  emitp(dst, mode);
1738  } else {
1740  emit(0xA3);
1741  emitp(dst, mode);
1742  // In 64-bit mode, need to zero extend the operand to 8 bytes.
1743  // See 2.2.1.4 in Intel64 and IA32 Architectures Software
1744  // Developer's Manual Volume 2.
1745  emitl(0);
1746  }
1747 }
1748 
1749 
1750 void Assembler::store_rax(ExternalReference ref) {
1751  store_rax(ref.address(), RelocInfo::EXTERNAL_REFERENCE);
1752 }
1753 
1754 
1755 void Assembler::testb(Register dst, Register src) {
1756  EnsureSpace ensure_space(this);
1757  if (src.low_bits() == 4) {
1758  emit_rex_32(src, dst);
1759  emit(0x84);
1760  emit_modrm(src, dst);
1761  } else {
1762  if (!dst.is_byte_register() || !src.is_byte_register()) {
1763  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1764  emit_rex_32(dst, src);
1765  }
1766  emit(0x84);
1767  emit_modrm(dst, src);
1768  }
1769 }
1770 
1771 
1772 void Assembler::testb(Register reg, Immediate mask) {
1773  DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
1774  EnsureSpace ensure_space(this);
1775  if (reg.is(rax)) {
1776  emit(0xA8);
1777  emit(mask.value_); // Low byte emitted.
1778  } else {
1779  if (!reg.is_byte_register()) {
1780  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1781  emit_rex_32(reg);
1782  }
1783  emit(0xF6);
1784  emit_modrm(0x0, reg);
1785  emit(mask.value_); // Low byte emitted.
1786  }
1787 }
1788 
1789 
1790 void Assembler::testb(const Operand& op, Immediate mask) {
1791  DCHECK(is_int8(mask.value_) || is_uint8(mask.value_));
1792  EnsureSpace ensure_space(this);
1793  emit_optional_rex_32(rax, op);
1794  emit(0xF6);
1795  emit_operand(rax, op); // Operation code 0
1796  emit(mask.value_); // Low byte emitted.
1797 }
1798 
1799 
1800 void Assembler::testb(const Operand& op, Register reg) {
1801  EnsureSpace ensure_space(this);
1802  if (!reg.is_byte_register()) {
1803  // Register is not one of al, bl, cl, dl. Its encoding needs REX.
1804  emit_rex_32(reg, op);
1805  } else {
1806  emit_optional_rex_32(reg, op);
1807  }
1808  emit(0x84);
1809  emit_operand(reg, op);
1810 }
1811 
1812 
1813 void Assembler::emit_test(Register dst, Register src, int size) {
1814  EnsureSpace ensure_space(this);
1815  if (src.low_bits() == 4) {
1816  emit_rex(src, dst, size);
1817  emit(0x85);
1818  emit_modrm(src, dst);
1819  } else {
1820  emit_rex(dst, src, size);
1821  emit(0x85);
1822  emit_modrm(dst, src);
1823  }
1824 }
1825 
1826 
1827 void Assembler::emit_test(Register reg, Immediate mask, int size) {
1828  // testl with a mask that fits in the low byte is exactly testb.
1829  if (is_uint8(mask.value_)) {
1830  testb(reg, mask);
1831  return;
1832  }
1833  EnsureSpace ensure_space(this);
1834  if (reg.is(rax)) {
1835  emit_rex(rax, size);
1836  emit(0xA9);
1837  emit(mask);
1838  } else {
1839  emit_rex(reg, size);
1840  emit(0xF7);
1841  emit_modrm(0x0, reg);
1842  emit(mask);
1843  }
1844 }
1845 
1846 
1847 void Assembler::emit_test(const Operand& op, Immediate mask, int size) {
1848  // testl with a mask that fits in the low byte is exactly testb.
1849  if (is_uint8(mask.value_)) {
1850  testb(op, mask);
1851  return;
1852  }
1853  EnsureSpace ensure_space(this);
1854  emit_rex(rax, op, size);
1855  emit(0xF7);
1856  emit_operand(rax, op); // Operation code 0
1857  emit(mask);
1858 }
1859 
1860 
1861 void Assembler::emit_test(const Operand& op, Register reg, int size) {
1862  EnsureSpace ensure_space(this);
1863  emit_rex(reg, op, size);
1864  emit(0x85);
1865  emit_operand(reg, op);
1866 }
1867 
1868 
1869 // FPU instructions.
1870 
1871 
1872 void Assembler::fld(int i) {
1873  EnsureSpace ensure_space(this);
1874  emit_farith(0xD9, 0xC0, i);
1875 }
1876 
1877 
1878 void Assembler::fld1() {
1879  EnsureSpace ensure_space(this);
1880  emit(0xD9);
1881  emit(0xE8);
1882 }
1883 
1884 
1885 void Assembler::fldz() {
1886  EnsureSpace ensure_space(this);
1887  emit(0xD9);
1888  emit(0xEE);
1889 }
1890 
1891 
1892 void Assembler::fldpi() {
1893  EnsureSpace ensure_space(this);
1894  emit(0xD9);
1895  emit(0xEB);
1896 }
1897 
1898 
1899 void Assembler::fldln2() {
1900  EnsureSpace ensure_space(this);
1901  emit(0xD9);
1902  emit(0xED);
1903 }
1904 
1905 
1906 void Assembler::fld_s(const Operand& adr) {
1907  EnsureSpace ensure_space(this);
1908  emit_optional_rex_32(adr);
1909  emit(0xD9);
1910  emit_operand(0, adr);
1911 }
1912 
1913 
1914 void Assembler::fld_d(const Operand& adr) {
1915  EnsureSpace ensure_space(this);
1916  emit_optional_rex_32(adr);
1917  emit(0xDD);
1918  emit_operand(0, adr);
1919 }
1920 
1921 
1922 void Assembler::fstp_s(const Operand& adr) {
1923  EnsureSpace ensure_space(this);
1924  emit_optional_rex_32(adr);
1925  emit(0xD9);
1926  emit_operand(3, adr);
1927 }
1928 
1929 
1930 void Assembler::fstp_d(const Operand& adr) {
1931  EnsureSpace ensure_space(this);
1932  emit_optional_rex_32(adr);
1933  emit(0xDD);
1934  emit_operand(3, adr);
1935 }
1936 
1937 
1938 void Assembler::fstp(int index) {
1939  DCHECK(is_uint3(index));
1940  EnsureSpace ensure_space(this);
1941  emit_farith(0xDD, 0xD8, index);
1942 }
1943 
1944 
1945 void Assembler::fild_s(const Operand& adr) {
1946  EnsureSpace ensure_space(this);
1947  emit_optional_rex_32(adr);
1948  emit(0xDB);
1949  emit_operand(0, adr);
1950 }
1951 
1952 
1953 void Assembler::fild_d(const Operand& adr) {
1954  EnsureSpace ensure_space(this);
1955  emit_optional_rex_32(adr);
1956  emit(0xDF);
1957  emit_operand(5, adr);
1958 }
1959 
1960 
1961 void Assembler::fistp_s(const Operand& adr) {
1962  EnsureSpace ensure_space(this);
1963  emit_optional_rex_32(adr);
1964  emit(0xDB);
1965  emit_operand(3, adr);
1966 }
1967 
1968 
1969 void Assembler::fisttp_s(const Operand& adr) {
1970  DCHECK(IsEnabled(SSE3));
1971  EnsureSpace ensure_space(this);
1972  emit_optional_rex_32(adr);
1973  emit(0xDB);
1974  emit_operand(1, adr);
1975 }
1976 
1977 
1978 void Assembler::fisttp_d(const Operand& adr) {
1979  DCHECK(IsEnabled(SSE3));
1980  EnsureSpace ensure_space(this);
1981  emit_optional_rex_32(adr);
1982  emit(0xDD);
1983  emit_operand(1, adr);
1984 }
1985 
1986 
1987 void Assembler::fist_s(const Operand& adr) {
1988  EnsureSpace ensure_space(this);
1989  emit_optional_rex_32(adr);
1990  emit(0xDB);
1991  emit_operand(2, adr);
1992 }
1993 
1994 
1995 void Assembler::fistp_d(const Operand& adr) {
1996  EnsureSpace ensure_space(this);
1997  emit_optional_rex_32(adr);
1998  emit(0xDF);
1999  emit_operand(7, adr);
2000 }
2001 
2002 
2003 void Assembler::fabs() {
2004  EnsureSpace ensure_space(this);
2005  emit(0xD9);
2006  emit(0xE1);
2007 }
2008 
2009 
2010 void Assembler::fchs() {
2011  EnsureSpace ensure_space(this);
2012  emit(0xD9);
2013  emit(0xE0);
2014 }
2015 
2016 
2017 void Assembler::fcos() {
2018  EnsureSpace ensure_space(this);
2019  emit(0xD9);
2020  emit(0xFF);
2021 }
2022 
2023 
2024 void Assembler::fsin() {
2025  EnsureSpace ensure_space(this);
2026  emit(0xD9);
2027  emit(0xFE);
2028 }
2029 
2030 
2031 void Assembler::fptan() {
2032  EnsureSpace ensure_space(this);
2033  emit(0xD9);
2034  emit(0xF2);
2035 }
2036 
2037 
2038 void Assembler::fyl2x() {
2039  EnsureSpace ensure_space(this);
2040  emit(0xD9);
2041  emit(0xF1);
2042 }
2043 
2044 
2045 void Assembler::f2xm1() {
2046  EnsureSpace ensure_space(this);
2047  emit(0xD9);
2048  emit(0xF0);
2049 }
2050 
2051 
2052 void Assembler::fscale() {
2053  EnsureSpace ensure_space(this);
2054  emit(0xD9);
2055  emit(0xFD);
2056 }
2057 
2058 
2059 void Assembler::fninit() {
2060  EnsureSpace ensure_space(this);
2061  emit(0xDB);
2062  emit(0xE3);
2063 }
2064 
2065 
2066 void Assembler::fadd(int i) {
2067  EnsureSpace ensure_space(this);
2068  emit_farith(0xDC, 0xC0, i);
2069 }
2070 
2071 
2072 void Assembler::fsub(int i) {
2073  EnsureSpace ensure_space(this);
2074  emit_farith(0xDC, 0xE8, i);
2075 }
2076 
2077 
2078 void Assembler::fisub_s(const Operand& adr) {
2079  EnsureSpace ensure_space(this);
2080  emit_optional_rex_32(adr);
2081  emit(0xDA);
2082  emit_operand(4, adr);
2083 }
2084 
2085 
2086 void Assembler::fmul(int i) {
2087  EnsureSpace ensure_space(this);
2088  emit_farith(0xDC, 0xC8, i);
2089 }
2090 
2091 
2092 void Assembler::fdiv(int i) {
2093  EnsureSpace ensure_space(this);
2094  emit_farith(0xDC, 0xF8, i);
2095 }
2096 
2097 
2098 void Assembler::faddp(int i) {
2099  EnsureSpace ensure_space(this);
2100  emit_farith(0xDE, 0xC0, i);
2101 }
2102 
2103 
2104 void Assembler::fsubp(int i) {
2105  EnsureSpace ensure_space(this);
2106  emit_farith(0xDE, 0xE8, i);
2107 }
2108 
2109 
2110 void Assembler::fsubrp(int i) {
2111  EnsureSpace ensure_space(this);
2112  emit_farith(0xDE, 0xE0, i);
2113 }
2114 
2115 
2116 void Assembler::fmulp(int i) {
2117  EnsureSpace ensure_space(this);
2118  emit_farith(0xDE, 0xC8, i);
2119 }
2120 
2121 
2122 void Assembler::fdivp(int i) {
2123  EnsureSpace ensure_space(this);
2124  emit_farith(0xDE, 0xF8, i);
2125 }
2126 
2127 
2128 void Assembler::fprem() {
2129  EnsureSpace ensure_space(this);
2130  emit(0xD9);
2131  emit(0xF8);
2132 }
2133 
2134 
2135 void Assembler::fprem1() {
2136  EnsureSpace ensure_space(this);
2137  emit(0xD9);
2138  emit(0xF5);
2139 }
2140 
2141 
2142 void Assembler::fxch(int i) {
2143  EnsureSpace ensure_space(this);
2144  emit_farith(0xD9, 0xC8, i);
2145 }
2146 
2147 
2148 void Assembler::fincstp() {
2149  EnsureSpace ensure_space(this);
2150  emit(0xD9);
2151  emit(0xF7);
2152 }
2153 
2154 
2155 void Assembler::ffree(int i) {
2156  EnsureSpace ensure_space(this);
2157  emit_farith(0xDD, 0xC0, i);
2158 }
2159 
2160 
2161 void Assembler::ftst() {
2162  EnsureSpace ensure_space(this);
2163  emit(0xD9);
2164  emit(0xE4);
2165 }
2166 
2167 
2168 void Assembler::fucomp(int i) {
2169  EnsureSpace ensure_space(this);
2170  emit_farith(0xDD, 0xE8, i);
2171 }
2172 
2173 
2174 void Assembler::fucompp() {
2175  EnsureSpace ensure_space(this);
2176  emit(0xDA);
2177  emit(0xE9);
2178 }
2179 
2180 
2181 void Assembler::fucomi(int i) {
2182  EnsureSpace ensure_space(this);
2183  emit(0xDB);
2184  emit(0xE8 + i);
2185 }
2186 
2187 
2188 void Assembler::fucomip() {
2189  EnsureSpace ensure_space(this);
2190  emit(0xDF);
2191  emit(0xE9);
2192 }
2193 
2194 
2195 void Assembler::fcompp() {
2196  EnsureSpace ensure_space(this);
2197  emit(0xDE);
2198  emit(0xD9);
2199 }
2200 
2201 
2202 void Assembler::fnstsw_ax() {
2203  EnsureSpace ensure_space(this);
2204  emit(0xDF);
2205  emit(0xE0);
2206 }
2207 
2208 
2209 void Assembler::fwait() {
2210  EnsureSpace ensure_space(this);
2211  emit(0x9B);
2212 }
2213 
2214 
2215 void Assembler::frndint() {
2216  EnsureSpace ensure_space(this);
2217  emit(0xD9);
2218  emit(0xFC);
2219 }
2220 
2221 
2222 void Assembler::fnclex() {
2223  EnsureSpace ensure_space(this);
2224  emit(0xDB);
2225  emit(0xE2);
2226 }
2227 
2228 
2229 void Assembler::sahf() {
2230  // TODO(X64): Test for presence. Not all 64-bit intel CPU's have sahf
2231  // in 64-bit mode. Test CpuID.
2232  DCHECK(IsEnabled(SAHF));
2233  EnsureSpace ensure_space(this);
2234  emit(0x9E);
2235 }
2236 
2237 
2238 void Assembler::emit_farith(int b1, int b2, int i) {
2239  DCHECK(is_uint8(b1) && is_uint8(b2)); // wrong opcode
2240  DCHECK(is_uint3(i)); // illegal stack offset
2241  emit(b1);
2242  emit(b2 + i);
2243 }
2244 
2245 
2246 // SSE operations.
2247 
2248 void Assembler::andps(XMMRegister dst, XMMRegister src) {
2249  EnsureSpace ensure_space(this);
2250  emit_optional_rex_32(dst, src);
2251  emit(0x0F);
2252  emit(0x54);
2253  emit_sse_operand(dst, src);
2254 }
2255 
2256 
2257 void Assembler::andps(XMMRegister dst, const Operand& src) {
2258  EnsureSpace ensure_space(this);
2259  emit_optional_rex_32(dst, src);
2260  emit(0x0F);
2261  emit(0x54);
2262  emit_sse_operand(dst, src);
2263 }
2264 
2265 
2266 void Assembler::orps(XMMRegister dst, XMMRegister src) {
2267  EnsureSpace ensure_space(this);
2268  emit_optional_rex_32(dst, src);
2269  emit(0x0F);
2270  emit(0x56);
2271  emit_sse_operand(dst, src);
2272 }
2273 
2274 
2275 void Assembler::orps(XMMRegister dst, const Operand& src) {
2276  EnsureSpace ensure_space(this);
2277  emit_optional_rex_32(dst, src);
2278  emit(0x0F);
2279  emit(0x56);
2280  emit_sse_operand(dst, src);
2281 }
2282 
2283 
2284 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
2285  EnsureSpace ensure_space(this);
2286  emit_optional_rex_32(dst, src);
2287  emit(0x0F);
2288  emit(0x57);
2289  emit_sse_operand(dst, src);
2290 }
2291 
2292 
2293 void Assembler::xorps(XMMRegister dst, const Operand& src) {
2294  EnsureSpace ensure_space(this);
2295  emit_optional_rex_32(dst, src);
2296  emit(0x0F);
2297  emit(0x57);
2298  emit_sse_operand(dst, src);
2299 }
2300 
2301 
2302 void Assembler::addps(XMMRegister dst, XMMRegister src) {
2303  EnsureSpace ensure_space(this);
2304  emit_optional_rex_32(dst, src);
2305  emit(0x0F);
2306  emit(0x58);
2307  emit_sse_operand(dst, src);
2308 }
2309 
2310 
2311 void Assembler::addps(XMMRegister dst, const Operand& src) {
2312  EnsureSpace ensure_space(this);
2313  emit_optional_rex_32(dst, src);
2314  emit(0x0F);
2315  emit(0x58);
2316  emit_sse_operand(dst, src);
2317 }
2318 
2319 
2320 void Assembler::subps(XMMRegister dst, XMMRegister src) {
2321  EnsureSpace ensure_space(this);
2322  emit_optional_rex_32(dst, src);
2323  emit(0x0F);
2324  emit(0x5C);
2325  emit_sse_operand(dst, src);
2326 }
2327 
2328 
2329 void Assembler::subps(XMMRegister dst, const Operand& src) {
2330  EnsureSpace ensure_space(this);
2331  emit_optional_rex_32(dst, src);
2332  emit(0x0F);
2333  emit(0x5C);
2334  emit_sse_operand(dst, src);
2335 }
2336 
2337 
2338 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
2339  EnsureSpace ensure_space(this);
2340  emit_optional_rex_32(dst, src);
2341  emit(0x0F);
2342  emit(0x59);
2343  emit_sse_operand(dst, src);
2344 }
2345 
2346 
2347 void Assembler::mulps(XMMRegister dst, const Operand& src) {
2348  EnsureSpace ensure_space(this);
2349  emit_optional_rex_32(dst, src);
2350  emit(0x0F);
2351  emit(0x59);
2352  emit_sse_operand(dst, src);
2353 }
2354 
2355 
2356 void Assembler::divps(XMMRegister dst, XMMRegister src) {
2357  EnsureSpace ensure_space(this);
2358  emit_optional_rex_32(dst, src);
2359  emit(0x0F);
2360  emit(0x5E);
2361  emit_sse_operand(dst, src);
2362 }
2363 
2364 
2365 void Assembler::divps(XMMRegister dst, const Operand& src) {
2366  EnsureSpace ensure_space(this);
2367  emit_optional_rex_32(dst, src);
2368  emit(0x0F);
2369  emit(0x5E);
2370  emit_sse_operand(dst, src);
2371 }
2372 
2373 
2374 // SSE 2 operations.
2375 
2376 void Assembler::movd(XMMRegister dst, Register src) {
2377  EnsureSpace ensure_space(this);
2378  emit(0x66);
2379  emit_optional_rex_32(dst, src);
2380  emit(0x0F);
2381  emit(0x6E);
2382  emit_sse_operand(dst, src);
2383 }
2384 
2385 
2386 void Assembler::movd(Register dst, XMMRegister src) {
2387  EnsureSpace ensure_space(this);
2388  emit(0x66);
2389  emit_optional_rex_32(src, dst);
2390  emit(0x0F);
2391  emit(0x7E);
2392  emit_sse_operand(src, dst);
2393 }
2394 
2395 
2396 void Assembler::movq(XMMRegister dst, Register src) {
2397  EnsureSpace ensure_space(this);
2398  emit(0x66);
2399  emit_rex_64(dst, src);
2400  emit(0x0F);
2401  emit(0x6E);
2402  emit_sse_operand(dst, src);
2403 }
2404 
2405 
2406 void Assembler::movq(Register dst, XMMRegister src) {
2407  EnsureSpace ensure_space(this);
2408  emit(0x66);
2409  emit_rex_64(src, dst);
2410  emit(0x0F);
2411  emit(0x7E);
2412  emit_sse_operand(src, dst);
2413 }
2414 
2415 
2416 void Assembler::movq(XMMRegister dst, XMMRegister src) {
2417  EnsureSpace ensure_space(this);
2418  if (dst.low_bits() == 4) {
2419  // Avoid unnecessary SIB byte.
2420  emit(0xf3);
2421  emit_optional_rex_32(dst, src);
2422  emit(0x0F);
2423  emit(0x7e);
2424  emit_sse_operand(dst, src);
2425  } else {
2426  emit(0x66);
2427  emit_optional_rex_32(src, dst);
2428  emit(0x0F);
2429  emit(0xD6);
2430  emit_sse_operand(src, dst);
2431  }
2432 }
2433 
2434 
2435 void Assembler::movdqa(const Operand& dst, XMMRegister src) {
2436  EnsureSpace ensure_space(this);
2437  emit(0x66);
2438  emit_rex_64(src, dst);
2439  emit(0x0F);
2440  emit(0x7F);
2441  emit_sse_operand(src, dst);
2442 }
2443 
2444 
2445 void Assembler::movdqa(XMMRegister dst, const Operand& src) {
2446  EnsureSpace ensure_space(this);
2447  emit(0x66);
2448  emit_rex_64(dst, src);
2449  emit(0x0F);
2450  emit(0x6F);
2451  emit_sse_operand(dst, src);
2452 }
2453 
2454 
2455 void Assembler::movdqu(const Operand& dst, XMMRegister src) {
2456  EnsureSpace ensure_space(this);
2457  emit(0xF3);
2458  emit_rex_64(src, dst);
2459  emit(0x0F);
2460  emit(0x7F);
2461  emit_sse_operand(src, dst);
2462 }
2463 
2464 
2465 void Assembler::movdqu(XMMRegister dst, const Operand& src) {
2466  EnsureSpace ensure_space(this);
2467  emit(0xF3);
2468  emit_rex_64(dst, src);
2469  emit(0x0F);
2470  emit(0x6F);
2471  emit_sse_operand(dst, src);
2472 }
2473 
2474 
2475 void Assembler::extractps(Register dst, XMMRegister src, byte imm8) {
2476  DCHECK(IsEnabled(SSE4_1));
2477  DCHECK(is_uint8(imm8));
2478  EnsureSpace ensure_space(this);
2479  emit(0x66);
2480  emit_optional_rex_32(src, dst);
2481  emit(0x0F);
2482  emit(0x3A);
2483  emit(0x17);
2484  emit_sse_operand(src, dst);
2485  emit(imm8);
2486 }
2487 
2488 
2489 void Assembler::movsd(const Operand& dst, XMMRegister src) {
2490  EnsureSpace ensure_space(this);
2491  emit(0xF2); // double
2492  emit_optional_rex_32(src, dst);
2493  emit(0x0F);
2494  emit(0x11); // store
2495  emit_sse_operand(src, dst);
2496 }
2497 
2498 
2499 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2500  EnsureSpace ensure_space(this);
2501  emit(0xF2); // double
2502  emit_optional_rex_32(dst, src);
2503  emit(0x0F);
2504  emit(0x10); // load
2505  emit_sse_operand(dst, src);
2506 }
2507 
2508 
2509 void Assembler::movsd(XMMRegister dst, const Operand& src) {
2510  EnsureSpace ensure_space(this);
2511  emit(0xF2); // double
2512  emit_optional_rex_32(dst, src);
2513  emit(0x0F);
2514  emit(0x10); // load
2515  emit_sse_operand(dst, src);
2516 }
2517 
2518 
2519 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2520  EnsureSpace ensure_space(this);
2521  if (src.low_bits() == 4) {
2522  // Try to avoid an unnecessary SIB byte.
2523  emit_optional_rex_32(src, dst);
2524  emit(0x0F);
2525  emit(0x29);
2526  emit_sse_operand(src, dst);
2527  } else {
2528  emit_optional_rex_32(dst, src);
2529  emit(0x0F);
2530  emit(0x28);
2531  emit_sse_operand(dst, src);
2532  }
2533 }
2534 
2535 
2536 void Assembler::shufps(XMMRegister dst, XMMRegister src, byte imm8) {
2537  DCHECK(is_uint8(imm8));
2538  EnsureSpace ensure_space(this);
2539  emit_optional_rex_32(src, dst);
2540  emit(0x0F);
2541  emit(0xC6);
2542  emit_sse_operand(dst, src);
2543  emit(imm8);
2544 }
2545 
2546 
2547 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2548  EnsureSpace ensure_space(this);
2549  if (src.low_bits() == 4) {
2550  // Try to avoid an unnecessary SIB byte.
2551  emit(0x66);
2552  emit_optional_rex_32(src, dst);
2553  emit(0x0F);
2554  emit(0x29);
2555  emit_sse_operand(src, dst);
2556  } else {
2557  emit(0x66);
2558  emit_optional_rex_32(dst, src);
2559  emit(0x0F);
2560  emit(0x28);
2561  emit_sse_operand(dst, src);
2562  }
2563 }
2564 
2565 
2566 void Assembler::movss(XMMRegister dst, const Operand& src) {
2567  EnsureSpace ensure_space(this);
2568  emit(0xF3); // single
2569  emit_optional_rex_32(dst, src);
2570  emit(0x0F);
2571  emit(0x10); // load
2572  emit_sse_operand(dst, src);
2573 }
2574 
2575 
2576 void Assembler::movss(const Operand& src, XMMRegister dst) {
2577  EnsureSpace ensure_space(this);
2578  emit(0xF3); // single
2579  emit_optional_rex_32(dst, src);
2580  emit(0x0F);
2581  emit(0x11); // store
2582  emit_sse_operand(dst, src);
2583 }
2584 
2585 
2586 void Assembler::psllq(XMMRegister reg, byte imm8) {
2587  EnsureSpace ensure_space(this);
2588  emit(0x66);
2589  emit(0x0F);
2590  emit(0x73);
2591  emit_sse_operand(rsi, reg); // rsi == 6
2592  emit(imm8);
2593 }
2594 
2595 
2596 void Assembler::cvttss2si(Register dst, const Operand& src) {
2597  EnsureSpace ensure_space(this);
2598  emit(0xF3);
2599  emit_optional_rex_32(dst, src);
2600  emit(0x0F);
2601  emit(0x2C);
2602  emit_operand(dst, src);
2603 }
2604 
2605 
2606 void Assembler::cvttss2si(Register dst, XMMRegister src) {
2607  EnsureSpace ensure_space(this);
2608  emit(0xF3);
2609  emit_optional_rex_32(dst, src);
2610  emit(0x0F);
2611  emit(0x2C);
2612  emit_sse_operand(dst, src);
2613 }
2614 
2615 
2616 void Assembler::cvttsd2si(Register dst, const Operand& src) {
2617  EnsureSpace ensure_space(this);
2618  emit(0xF2);
2619  emit_optional_rex_32(dst, src);
2620  emit(0x0F);
2621  emit(0x2C);
2622  emit_operand(dst, src);
2623 }
2624 
2625 
2626 void Assembler::cvttsd2si(Register dst, XMMRegister src) {
2627  EnsureSpace ensure_space(this);
2628  emit(0xF2);
2629  emit_optional_rex_32(dst, src);
2630  emit(0x0F);
2631  emit(0x2C);
2632  emit_sse_operand(dst, src);
2633 }
2634 
2635 
2636 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
2637  EnsureSpace ensure_space(this);
2638  emit(0xF2);
2639  emit_rex_64(dst, src);
2640  emit(0x0F);
2641  emit(0x2C);
2642  emit_sse_operand(dst, src);
2643 }
2644 
2645 
2646 void Assembler::cvttsd2siq(Register dst, const Operand& src) {
2647  EnsureSpace ensure_space(this);
2648  emit(0xF2);
2649  emit_rex_64(dst, src);
2650  emit(0x0F);
2651  emit(0x2C);
2652  emit_sse_operand(dst, src);
2653 }
2654 
2655 
2656 void Assembler::cvtlsi2sd(XMMRegister dst, const Operand& src) {
2657  EnsureSpace ensure_space(this);
2658  emit(0xF2);
2659  emit_optional_rex_32(dst, src);
2660  emit(0x0F);
2661  emit(0x2A);
2662  emit_sse_operand(dst, src);
2663 }
2664 
2665 
2666 void Assembler::cvtlsi2sd(XMMRegister dst, Register src) {
2667  EnsureSpace ensure_space(this);
2668  emit(0xF2);
2669  emit_optional_rex_32(dst, src);
2670  emit(0x0F);
2671  emit(0x2A);
2672  emit_sse_operand(dst, src);
2673 }
2674 
2675 
2676 void Assembler::cvtlsi2ss(XMMRegister dst, Register src) {
2677  EnsureSpace ensure_space(this);
2678  emit(0xF3);
2679  emit_optional_rex_32(dst, src);
2680  emit(0x0F);
2681  emit(0x2A);
2682  emit_sse_operand(dst, src);
2683 }
2684 
2685 
2686 void Assembler::cvtqsi2sd(XMMRegister dst, Register src) {
2687  EnsureSpace ensure_space(this);
2688  emit(0xF2);
2689  emit_rex_64(dst, src);
2690  emit(0x0F);
2691  emit(0x2A);
2692  emit_sse_operand(dst, src);
2693 }
2694 
2695 
2696 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
2697  EnsureSpace ensure_space(this);
2698  emit(0xF3);
2699  emit_optional_rex_32(dst, src);
2700  emit(0x0F);
2701  emit(0x5A);
2702  emit_sse_operand(dst, src);
2703 }
2704 
2705 
2706 void Assembler::cvtss2sd(XMMRegister dst, const Operand& src) {
2707  EnsureSpace ensure_space(this);
2708  emit(0xF3);
2709  emit_optional_rex_32(dst, src);
2710  emit(0x0F);
2711  emit(0x5A);
2712  emit_sse_operand(dst, src);
2713 }
2714 
2715 
2716 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
2717  EnsureSpace ensure_space(this);
2718  emit(0xF2);
2719  emit_optional_rex_32(dst, src);
2720  emit(0x0F);
2721  emit(0x5A);
2722  emit_sse_operand(dst, src);
2723 }
2724 
2725 
2726 void Assembler::cvtsd2si(Register dst, XMMRegister src) {
2727  EnsureSpace ensure_space(this);
2728  emit(0xF2);
2729  emit_optional_rex_32(dst, src);
2730  emit(0x0F);
2731  emit(0x2D);
2732  emit_sse_operand(dst, src);
2733 }
2734 
2735 
2736 void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
2737  EnsureSpace ensure_space(this);
2738  emit(0xF2);
2739  emit_rex_64(dst, src);
2740  emit(0x0F);
2741  emit(0x2D);
2742  emit_sse_operand(dst, src);
2743 }
2744 
2745 
2746 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
2747  EnsureSpace ensure_space(this);
2748  emit(0xF2);
2749  emit_optional_rex_32(dst, src);
2750  emit(0x0F);
2751  emit(0x58);
2752  emit_sse_operand(dst, src);
2753 }
2754 
2755 
2756 void Assembler::addsd(XMMRegister dst, const Operand& src) {
2757  EnsureSpace ensure_space(this);
2758  emit(0xF2);
2759  emit_optional_rex_32(dst, src);
2760  emit(0x0F);
2761  emit(0x58);
2762  emit_sse_operand(dst, src);
2763 }
2764 
2765 
2766 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2767  EnsureSpace ensure_space(this);
2768  emit(0xF2);
2769  emit_optional_rex_32(dst, src);
2770  emit(0x0F);
2771  emit(0x59);
2772  emit_sse_operand(dst, src);
2773 }
2774 
2775 
2776 void Assembler::mulsd(XMMRegister dst, const Operand& src) {
2777  EnsureSpace ensure_space(this);
2778  emit(0xF2);
2779  emit_optional_rex_32(dst, src);
2780  emit(0x0F);
2781  emit(0x59);
2782  emit_sse_operand(dst, src);
2783 }
2784 
2785 
2786 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
2787  EnsureSpace ensure_space(this);
2788  emit(0xF2);
2789  emit_optional_rex_32(dst, src);
2790  emit(0x0F);
2791  emit(0x5C);
2792  emit_sse_operand(dst, src);
2793 }
2794 
2795 
2796 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2797  EnsureSpace ensure_space(this);
2798  emit(0xF2);
2799  emit_optional_rex_32(dst, src);
2800  emit(0x0F);
2801  emit(0x5E);
2802  emit_sse_operand(dst, src);
2803 }
2804 
2805 
2806 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
2807  EnsureSpace ensure_space(this);
2808  emit(0x66);
2809  emit_optional_rex_32(dst, src);
2810  emit(0x0F);
2811  emit(0x54);
2812  emit_sse_operand(dst, src);
2813 }
2814 
2815 
2816 void Assembler::orpd(XMMRegister dst, XMMRegister src) {
2817  EnsureSpace ensure_space(this);
2818  emit(0x66);
2819  emit_optional_rex_32(dst, src);
2820  emit(0x0F);
2821  emit(0x56);
2822  emit_sse_operand(dst, src);
2823 }
2824 
2825 
2826 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
2827  EnsureSpace ensure_space(this);
2828  emit(0x66);
2829  emit_optional_rex_32(dst, src);
2830  emit(0x0F);
2831  emit(0x57);
2832  emit_sse_operand(dst, src);
2833 }
2834 
2835 
2836 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
2837  EnsureSpace ensure_space(this);
2838  emit(0xF2);
2839  emit_optional_rex_32(dst, src);
2840  emit(0x0F);
2841  emit(0x51);
2842  emit_sse_operand(dst, src);
2843 }
2844 
2845 
2846 void Assembler::sqrtsd(XMMRegister dst, const Operand& src) {
2847  EnsureSpace ensure_space(this);
2848  emit(0xF2);
2849  emit_optional_rex_32(dst, src);
2850  emit(0x0F);
2851  emit(0x51);
2852  emit_sse_operand(dst, src);
2853 }
2854 
2855 
2856 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
2857  EnsureSpace ensure_space(this);
2858  emit(0x66);
2859  emit_optional_rex_32(dst, src);
2860  emit(0x0f);
2861  emit(0x2e);
2862  emit_sse_operand(dst, src);
2863 }
2864 
2865 
2866 void Assembler::ucomisd(XMMRegister dst, const Operand& src) {
2867  EnsureSpace ensure_space(this);
2868  emit(0x66);
2869  emit_optional_rex_32(dst, src);
2870  emit(0x0f);
2871  emit(0x2e);
2872  emit_sse_operand(dst, src);
2873 }
2874 
2875 
2876 void Assembler::cmpltsd(XMMRegister dst, XMMRegister src) {
2877  EnsureSpace ensure_space(this);
2878  emit(0xF2);
2879  emit_optional_rex_32(dst, src);
2880  emit(0x0F);
2881  emit(0xC2);
2882  emit_sse_operand(dst, src);
2883  emit(0x01); // LT == 1
2884 }
2885 
2886 
2887 void Assembler::roundsd(XMMRegister dst, XMMRegister src,
2888  Assembler::RoundingMode mode) {
2889  DCHECK(IsEnabled(SSE4_1));
2890  EnsureSpace ensure_space(this);
2891  emit(0x66);
2892  emit_optional_rex_32(dst, src);
2893  emit(0x0f);
2894  emit(0x3a);
2895  emit(0x0b);
2896  emit_sse_operand(dst, src);
2897  // Mask precision exeption.
2898  emit(static_cast<byte>(mode) | 0x8);
2899 }
2900 
2901 
2902 void Assembler::movmskpd(Register dst, XMMRegister src) {
2903  EnsureSpace ensure_space(this);
2904  emit(0x66);
2905  emit_optional_rex_32(dst, src);
2906  emit(0x0f);
2907  emit(0x50);
2908  emit_sse_operand(dst, src);
2909 }
2910 
2911 
2912 void Assembler::movmskps(Register dst, XMMRegister src) {
2913  EnsureSpace ensure_space(this);
2914  emit_optional_rex_32(dst, src);
2915  emit(0x0f);
2916  emit(0x50);
2917  emit_sse_operand(dst, src);
2918 }
2919 
2920 
2921 void Assembler::emit_sse_operand(XMMRegister reg, const Operand& adr) {
2922  Register ireg = { reg.code() };
2923  emit_operand(ireg, adr);
2924 }
2925 
2926 
2927 void Assembler::emit_sse_operand(Register reg, const Operand& adr) {
2928  Register ireg = {reg.code()};
2929  emit_operand(ireg, adr);
2930 }
2931 
2932 
2933 void Assembler::emit_sse_operand(XMMRegister dst, XMMRegister src) {
2934  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
2935 }
2936 
2937 
2938 void Assembler::emit_sse_operand(XMMRegister dst, Register src) {
2939  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
2940 }
2941 
2942 
2943 void Assembler::emit_sse_operand(Register dst, XMMRegister src) {
2944  emit(0xC0 | (dst.low_bits() << 3) | src.low_bits());
2945 }
2946 
2947 
2948 void Assembler::db(uint8_t data) {
2949  EnsureSpace ensure_space(this);
2950  emit(data);
2951 }
2952 
2953 
2954 void Assembler::dd(uint32_t data) {
2955  EnsureSpace ensure_space(this);
2956  emitl(data);
2957 }
2958 
2959 
2960 // Relocation information implementations.
2961 
2962 void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) {
2963  DCHECK(!RelocInfo::IsNone(rmode));
2964  // Don't record external references unless the heap will be serialized.
2965  if (rmode == RelocInfo::EXTERNAL_REFERENCE &&
2966  !serializer_enabled() && !emit_debug_code()) {
2967  return;
2968  } else if (rmode == RelocInfo::CODE_AGE_SEQUENCE) {
2969  // Don't record psuedo relocation info for code age sequence mode.
2970  return;
2971  }
2972  RelocInfo rinfo(pc_, rmode, data, NULL);
2973  reloc_info_writer.Write(&rinfo);
2974 }
2975 
2976 
2977 void Assembler::RecordJSReturn() {
2978  positions_recorder()->WriteRecordedPositions();
2979  EnsureSpace ensure_space(this);
2980  RecordRelocInfo(RelocInfo::JS_RETURN);
2981 }
2982 
2983 
2984 void Assembler::RecordDebugBreakSlot() {
2985  positions_recorder()->WriteRecordedPositions();
2986  EnsureSpace ensure_space(this);
2987  RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT);
2988 }
2989 
2990 
2991 void Assembler::RecordComment(const char* msg, bool force) {
2992  if (FLAG_code_comments || force) {
2993  EnsureSpace ensure_space(this);
2994  RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg));
2995  }
2996 }
2997 
2998 
2999 Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) {
3000  // No out-of-line constant pool support.
3001  DCHECK(!FLAG_enable_ool_constant_pool);
3002  return isolate->factory()->empty_constant_pool_array();
3003 }
3004 
3005 
3006 void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) {
3007  // No out-of-line constant pool support.
3008  DCHECK(!FLAG_enable_ool_constant_pool);
3009  return;
3010 }
3011 
3012 
3013 const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask |
3015  1 << RelocInfo::INTERNAL_REFERENCE |
3016  1 << RelocInfo::CODE_AGE_SEQUENCE;
3017 
3018 
3019 bool RelocInfo::IsCodedSpecially() {
3020  // The deserializer needs to know whether a pointer is specially coded. Being
3021  // specially coded on x64 means that it is a relative 32 bit address, as used
3022  // by branch instructions.
3023  return (1 << rmode_) & kApplyMask;
3024 }
3025 
3026 
3027 bool RelocInfo::IsInConstantPool() {
3028  return false;
3029 }
3030 
3031 
3032 } } // namespace v8::internal
3033 
3034 #endif // V8_TARGET_ARCH_X64
static const int kCallSequenceLength
static RelocInfo::Mode RelocInfoNone()
static void FlushICache(void *start, size_t size)
static unsigned supported_
Definition: assembler.h:205
static void PrintFeatures()
static void ProbeImpl(bool cross_compile)
Operand(Register reg, Shift shift=LSL, unsigned shift_amount=0)
void PatchCode(byte *instructions, int instruction_count)
void PatchCodeWithCall(Address target, int guard_bytes)
enable harmony numeric enable harmony object literal extensions Optimize object size
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
enable harmony numeric enable harmony object literal extensions Optimize object Array shift
#define CHECK(condition)
Definition: logging.h:36
#define FATAL(msg)
Definition: logging.h:26
#define DCHECK(condition)
Definition: logging.h:205
#define DCHECK_EQ(v1, v2)
Definition: logging.h:206
int int32_t
Definition: unicode.cc:24
bool IsPowerOfTwo32(uint32_t value)
Definition: bits.h:77
void DeleteArray(T *array)
Definition: allocation.h:68
const int kPointerSize
Definition: globals.h:129
const Register kScratchRegister
const Register rsi
void MemMove(void *dest, const void *src, size_t size)
Definition: utils.h:353
const Register rbp
const Register r12
const int kInt64Size
Definition: globals.h:126
const int kInt32Size
Definition: globals.h:125
byte * Address
Definition: globals.h:101
const Register r13
const Register rax
void FatalProcessOutOfMemory(const char *message)
const Register rsp
const int kNumRegisters
Definition: constants-arm.h:34
Debugger support for the V8 JavaScript engine.
Definition: accessors.cc:20
static const uint16_t * Align(const uint16_t *chars)
Definition: api.cc:4266
#define RUNTIME_ENTRY(name, nargs, ressize)
static const int kAllocationIndexByRegisterCode[kNumRegisters]
static const int kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters]