V8 Project
code-stubs-arm.h
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1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_ARM_CODE_STUBS_ARM_H_
6 #define V8_ARM_CODE_STUBS_ARM_H_
7 
8 namespace v8 {
9 namespace internal {
10 
11 
12 void ArrayNativeCode(MacroAssembler* masm, Label* call_generic_code);
13 
14 
15 class StringHelper : public AllStatic {
16  public:
17  // Generate code for copying a large number of characters. This function
18  // is allowed to spend extra time setting up conditions to make copying
19  // faster. Copying of overlapping regions is not supported.
20  // Dest register ends at the position after the last character written.
22  Register dest,
23  Register src,
24  Register count,
25  Register scratch,
26  String::Encoding encoding);
27 
28  // Compares two flat one-byte strings and returns result in r0.
30  MacroAssembler* masm, Register left, Register right, Register scratch1,
31  Register scratch2, Register scratch3, Register scratch4);
32 
33  // Compares two flat one-byte strings for equality and returns result in r0.
35  Register left, Register right,
36  Register scratch1,
37  Register scratch2,
38  Register scratch3);
39 
40  private:
42  MacroAssembler* masm, Register left, Register right, Register length,
43  Register scratch1, Register scratch2, Label* chars_not_equal);
44 
46 };
47 
48 
49 // This stub can convert a signed int32 to a heap number (double). It does
50 // not work for int32s that are in Smi range! No GC occurs during this stub
51 // so you don't have to set up the frame.
53  public:
56  : PlatformCodeStub(isolate) {
57  minor_key_ = IntRegisterBits::encode(the_int.code()) |
60  }
61 
63 
64  private:
65  Register the_int() const {
66  return Register::from_code(IntRegisterBits::decode(minor_key_));
67  }
68 
71  }
72 
73  Register scratch() const {
75  }
76 
77  // Minor key encoding in 16 bits.
78  class IntRegisterBits: public BitField<int, 0, 4> {};
79  class HeapNumberRegisterBits: public BitField<int, 4, 4> {};
80  class ScratchRegisterBits: public BitField<int, 8, 4> {};
81 
83  DEFINE_PLATFORM_CODE_STUB(WriteInt32ToHeapNumber, PlatformCodeStub);
84 };
85 
86 
88  public:
90  Register object,
94  SaveFPRegsMode fp_mode)
95  : PlatformCodeStub(isolate),
96  regs_(object, // An input reg.
97  address, // An input reg.
98  value) { // One scratch reg.
99  minor_key_ = ObjectBits::encode(object.code()) |
104  }
105 
107  : PlatformCodeStub(key, isolate), regs_(object(), address(), value()) {}
108 
109  enum Mode {
113  };
114 
115  virtual bool SometimesSetsUpAFrame() { return false; }
116 
117  static void PatchBranchIntoNop(MacroAssembler* masm, int pos) {
118  masm->instr_at_put(pos, (masm->instr_at(pos) & ~B27) | (B24 | B20));
120  }
121 
122  static void PatchNopIntoBranch(MacroAssembler* masm, int pos) {
123  masm->instr_at_put(pos, (masm->instr_at(pos) & ~(B24 | B20)) | B27);
124  DCHECK(Assembler::IsBranch(masm->instr_at(pos)));
125  }
126 
127  static Mode GetMode(Code* stub) {
128  Instr first_instruction = Assembler::instr_at(stub->instruction_start());
129  Instr second_instruction = Assembler::instr_at(stub->instruction_start() +
131 
132  if (Assembler::IsBranch(first_instruction)) {
133  return INCREMENTAL;
134  }
135 
136  DCHECK(Assembler::IsTstImmediate(first_instruction));
137 
138  if (Assembler::IsBranch(second_instruction)) {
139  return INCREMENTAL_COMPACTION;
140  }
141 
142  DCHECK(Assembler::IsTstImmediate(second_instruction));
143 
144  return STORE_BUFFER_ONLY;
145  }
146 
147  static void Patch(Code* stub, Mode mode) {
148  MacroAssembler masm(NULL,
149  stub->instruction_start(),
150  stub->instruction_size());
151  switch (mode) {
152  case STORE_BUFFER_ONLY:
153  DCHECK(GetMode(stub) == INCREMENTAL ||
155  PatchBranchIntoNop(&masm, 0);
157  break;
158  case INCREMENTAL:
159  DCHECK(GetMode(stub) == STORE_BUFFER_ONLY);
160  PatchNopIntoBranch(&masm, 0);
161  break;
163  DCHECK(GetMode(stub) == STORE_BUFFER_ONLY);
165  break;
166  }
167  DCHECK(GetMode(stub) == mode);
170  }
171 
173 
174  private:
175  // This is a helper class for freeing up 3 scratch registers. The input is
176  // two registers that must be preserved and one scratch register provided by
177  // the caller.
179  public:
183  : object_(object),
184  address_(address),
186  DCHECK(!AreAliased(scratch0, object, address, no_reg));
188  }
189 
190  void Save(MacroAssembler* masm) {
192  // We don't have to save scratch0_ because it was given to us as
193  // a scratch register.
194  masm->push(scratch1_);
195  }
196 
197  void Restore(MacroAssembler* masm) {
198  masm->pop(scratch1_);
199  }
200 
201  // If we have to call into C then we need to save and restore all caller-
202  // saved registers that were not already preserved. The scratch registers
203  // will be restored by other means so we don't bother pushing them here.
205  masm->stm(db_w, sp, (kCallerSaved | lr.bit()) & ~scratch1_.bit());
206  if (mode == kSaveFPRegs) {
207  masm->SaveFPRegs(sp, scratch0_);
208  }
209  }
210 
213  if (mode == kSaveFPRegs) {
214  masm->RestoreFPRegs(sp, scratch0_);
215  }
216  masm->ldm(ia_w, sp, (kCallerSaved | lr.bit()) & ~scratch1_.bit());
217  }
218 
219  inline Register object() { return object_; }
220  inline Register address() { return address_; }
221  inline Register scratch0() { return scratch0_; }
222  inline Register scratch1() { return scratch1_; }
223 
224  private:
229 
230  friend class RecordWriteStub;
231  };
232 
236  };
237 
238  virtual inline Major MajorKey() const FINAL OVERRIDE { return RecordWrite; }
239 
240  virtual void Generate(MacroAssembler* masm) OVERRIDE;
243  MacroAssembler* masm,
245  Mode mode);
247 
248  void Activate(Code* code) {
250  }
251 
252  Register object() const {
253  return Register::from_code(ObjectBits::decode(minor_key_));
254  }
255 
256  Register value() const {
257  return Register::from_code(ValueBits::decode(minor_key_));
258  }
259 
260  Register address() const {
261  return Register::from_code(AddressBits::decode(minor_key_));
262  }
263 
265  return RememberedSetActionBits::decode(minor_key_);
266  }
267 
269  return SaveFPRegsModeBits::decode(minor_key_);
270  }
271 
272  class ObjectBits: public BitField<int, 0, 4> {};
273  class ValueBits: public BitField<int, 4, 4> {};
274  class AddressBits: public BitField<int, 8, 4> {};
275  class RememberedSetActionBits: public BitField<RememberedSetAction, 12, 1> {};
276  class SaveFPRegsModeBits: public BitField<SaveFPRegsMode, 13, 1> {};
277 
278  Label slow_;
280 
282 };
283 
284 
285 // Trampoline stub to call into native code. To call safely into native code
286 // in the presence of compacting GC (which can move code objects) we need to
287 // keep the code which called into native pinned in the memory. Currently the
288 // simplest approach is to generate such stub early enough so it can never be
289 // moved by GC
291  public:
292  explicit DirectCEntryStub(Isolate* isolate) : PlatformCodeStub(isolate) {}
293  void GenerateCall(MacroAssembler* masm, Register target);
294 
295  private:
296  bool NeedsImmovableCode() { return true; }
297 
300 };
301 
302 
304  public:
306 
308  : PlatformCodeStub(isolate) {
309  minor_key_ = LookupModeBits::encode(mode);
310  }
311 
313  Label* miss,
314  Label* done,
315  Register receiver,
316  Register properties,
318  Register scratch0);
319 
321  Label* miss,
322  Label* done,
323  Register elements,
324  Register name,
325  Register r0,
326  Register r1);
327 
328  virtual bool SometimesSetsUpAFrame() { return false; }
329 
330  private:
331  static const int kInlinedProbes = 4;
332  static const int kTotalProbes = 20;
333 
334  static const int kCapacityOffset =
337 
338  static const int kElementsStartOffset =
341 
342  LookupMode mode() const { return LookupModeBits::decode(minor_key_); }
343 
344  class LookupModeBits: public BitField<LookupMode, 0, 1> {};
345 
348 };
349 
350 } } // namespace v8::internal
351 
352 #endif // V8_ARM_CODE_STUBS_ARM_H_
static const int kInstrSize
void stm(BlockAddrMode am, Register base, RegList src, Condition cond=al)
static bool IsTstImmediate(Instr instr)
void instr_at_put(int pos, Instr instr)
static bool IsBranch(Instr instr)
void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond=al)
static U encode(T value)
Definition: utils.h:217
static T decode(U value)
Definition: utils.h:228
int instruction_size() const
byte * instruction_start()
Definition: objects-inl.h:6176
static void FlushICache(void *start, size_t size)
DirectCEntryStub(Isolate *isolate)
void GenerateCall(MacroAssembler *masm, Register target)
DEFINE_PLATFORM_CODE_STUB(DirectCEntry, PlatformCodeStub)
Source to read snapshot and builtins files from.
Definition: lithium-arm.h:372
static const int kHeaderSize
Definition: objects.h:2393
static const int kElementsStartIndex
Definition: objects.h:3274
static const int kCapacityIndex
Definition: objects.h:3272
Heap * GetHeap() const
Definition: objects-inl.h:1379
IncrementalMarking * incremental_marking()
Definition: heap.h:1205
void RestoreFPRegs(Register location, Register scratch)
void SaveFPRegs(Register location, Register scratch)
NameDictionaryLookupStub(Isolate *isolate, LookupMode mode)
static void GeneratePositiveLookup(MacroAssembler *masm, Label *miss, Label *done, Register elements, Register name, Register r0, Register r1)
DEFINE_PLATFORM_CODE_STUB(NameDictionaryLookup, PlatformCodeStub)
static void GenerateNegativeLookup(MacroAssembler *masm, Label *miss, Label *done, Register receiver, Register properties, Handle< Name > name, Register scratch0)
void SaveCallerSaveRegisters(MacroAssembler *masm, SaveFPRegsMode mode)
RegisterAllocation(Register object, Register address, Register scratch0)
void RestoreCallerSaveRegisters(MacroAssembler *masm, SaveFPRegsMode mode)
void GenerateIncremental(MacroAssembler *masm, Mode mode)
void InformIncrementalMarker(MacroAssembler *masm)
RememberedSetAction remembered_set_action() const
static void PatchBranchIntoNop(MacroAssembler *masm, int pos)
static void PatchNopIntoBranch(MacroAssembler *masm, int pos)
SaveFPRegsMode save_fp_regs_mode() const
RecordWriteStub(Isolate *isolate, Register object, Register value, Register address, RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode)
RecordWriteStub(uint32_t key, Isolate *isolate)
virtual Major MajorKey() const FINAL OVERRIDE
void CheckNeedsToInformIncrementalMarker(MacroAssembler *masm, OnNoNeedToInformIncrementalMarker on_no_need, Mode mode)
DISALLOW_COPY_AND_ASSIGN(RecordWriteStub)
static void Patch(Code *stub, Mode mode)
virtual bool SometimesSetsUpAFrame()
static Mode GetMode(Code *stub)
virtual void Generate(MacroAssembler *masm) OVERRIDE
static void GenerateOneByteCharsCompareLoop(MacroAssembler *masm, Register left, Register right, Register length, Register scratch1, Register scratch2, Label *chars_not_equal)
DISALLOW_IMPLICIT_CONSTRUCTORS(StringHelper)
static void GenerateCompareFlatOneByteStrings(MacroAssembler *masm, Register left, Register right, Register scratch1, Register scratch2, Register scratch3, Register scratch4)
static void GenerateCopyCharacters(MacroAssembler *masm, Register dest, Register src, Register count, Register scratch, String::Encoding encoding)
static void GenerateFlatOneByteStringEquals(MacroAssembler *masm, Register left, Register right, Register scratch1, Register scratch2, Register scratch3)
DEFINE_PLATFORM_CODE_STUB(WriteInt32ToHeapNumber, PlatformCodeStub)
static void GenerateFixedRegStubsAheadOfTime(Isolate *isolate)
WriteInt32ToHeapNumberStub(Isolate *isolate, Register the_int, Register the_heap_number, Register scratch)
#define OVERRIDE
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
Definition: logging.h:205
const int kPointerSize
Definition: globals.h:129
bool AreAliased(const CPURegister &reg1, const CPURegister &reg2, const CPURegister &reg3=NoReg, const CPURegister &reg4=NoReg, const CPURegister &reg5=NoReg, const CPURegister &reg6=NoReg, const CPURegister &reg7=NoReg, const CPURegister &reg8=NoReg)
const Register r0
void ArrayNativeCode(MacroAssembler *masm, Label *call_generic_code)
const Register sp
const Register lr
const Register r1
const Register no_reg
Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2=no_reg, Register reg3=no_reg, Register reg4=no_reg, Register reg5=no_reg, Register reg6=no_reg)
const RegList kCallerSaved
Definition: frames-arm.h:50
Debugger support for the V8 JavaScript engine.
Definition: accessors.cc:20
static Register from_code(int code)