V8 Project
constants-arm.cc
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1 // Copyright 2009 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #include "src/v8.h"
6 
7 #if V8_TARGET_ARCH_ARM
8 
10 
11 
12 namespace v8 {
13 namespace internal {
14 
15 double Instruction::DoubleImmedVmov() const {
16  // Reconstruct a double from the immediate encoded in the vmov instruction.
17  //
18  // instruction: [xxxxxxxx,xxxxabcd,xxxxxxxx,xxxxefgh]
19  // double: [aBbbbbbb,bbcdefgh,00000000,00000000,
20  // 00000000,00000000,00000000,00000000]
21  //
22  // where B = ~b. Only the high 16 bits are affected.
23  uint64_t high16;
24  high16 = (Bits(17, 16) << 4) | Bits(3, 0); // xxxxxxxx,xxcdefgh.
25  high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx.
26  high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx.
27  high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx.
28 
29  uint64_t imm = high16 << 48;
30  double d;
31  memcpy(&d, &imm, 8);
32  return d;
33 }
34 
35 
36 // These register names are defined in a way to match the native disassembler
37 // formatting. See for example the command "objdump -d <binary file>".
38 const char* Registers::names_[kNumRegisters] = {
39  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
40  "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc",
41 };
42 
43 
44 // List of alias names which can be used when referring to ARM registers.
45 const Registers::RegisterAlias Registers::aliases_[] = {
46  {10, "sl"},
47  {11, "r11"},
48  {12, "r12"},
49  {13, "r13"},
50  {14, "r14"},
51  {15, "r15"},
52  {kNoRegister, NULL}
53 };
54 
55 
56 const char* Registers::Name(int reg) {
57  const char* result;
58  if ((0 <= reg) && (reg < kNumRegisters)) {
59  result = names_[reg];
60  } else {
61  result = "noreg";
62  }
63  return result;
64 }
65 
66 
67 // Support for VFP registers s0 to s31 (d0 to d15) and d16-d31.
68 // Note that "sN:sM" is the same as "dN/2" up to d15.
69 // These register names are defined in a way to match the native disassembler
70 // formatting. See for example the command "objdump -d <binary file>".
72  "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
73  "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
74  "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
75  "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
76  "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
77  "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
78  "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
79  "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"
80 };
81 
82 
83 const char* VFPRegisters::Name(int reg, bool is_double) {
84  DCHECK((0 <= reg) && (reg < kNumVFPRegisters));
85  return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)];
86 }
87 
88 
89 int VFPRegisters::Number(const char* name, bool* is_double) {
90  for (int i = 0; i < kNumVFPRegisters; i++) {
91  if (strcmp(names_[i], name) == 0) {
92  if (i < kNumVFPSingleRegisters) {
93  *is_double = false;
94  return i;
95  } else {
96  *is_double = true;
97  return i - kNumVFPSingleRegisters;
98  }
99  }
100  }
101 
102  // No register with the requested name found.
103  return kNoRegister;
104 }
105 
106 
107 int Registers::Number(const char* name) {
108  // Look through the canonical names.
109  for (int i = 0; i < kNumRegisters; i++) {
110  if (strcmp(names_[i], name) == 0) {
111  return i;
112  }
113  }
114 
115  // Look through the alias names.
116  int i = 0;
117  while (aliases_[i].reg != kNoRegister) {
118  if (strcmp(aliases_[i].name, name) == 0) {
119  return aliases_[i].reg;
120  }
121  i++;
122  }
123 
124  // No register with the requested name found.
125  return kNoRegister;
126 }
127 
128 
129 } } // namespace v8::internal
130 
131 #endif // V8_TARGET_ARCH_ARM
double DoubleImmedVmov() const
int Bits(int hi, int lo) const
int Bit(int nr) const
static int Number(const char *name)
static const RegisterAlias aliases_[]
static const char * names_[kNumRegisters]
static const char * Name(int reg)
static const char * names_[kNumVFPRegisters]
static int Number(const char *name, bool *is_double)
static const char * Name(int reg, bool is_double)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
Definition: logging.h:205
const int kNumVFPRegisters
Definition: constants-arm.h:39
const int kNoRegister
Definition: constants-arm.h:43
const int kNumVFPSingleRegisters
Definition: constants-arm.h:37
const int kNumRegisters
Definition: constants-arm.h:34
Debugger support for the V8 JavaScript engine.
Definition: accessors.cc:20