7 #if V8_TARGET_ARCH_ARM64
15 #define __ ACCESS_MASM(masm_)
18 void DelayedMasm::StackSlotMove(LOperand* src, LOperand* dst) {
19 DCHECK(src->IsStackSlot());
20 DCHECK(dst->IsStackSlot());
21 MemOperand src_operand = cgen_->ToMemOperand(src);
22 MemOperand dst_operand = cgen_->ToMemOperand(dst);
23 if (pending_ == kStackSlotMove) {
24 DCHECK(pending_pc_ == masm_->pc_offset());
25 UseScratchRegisterScope scope(masm_);
31 __ Ldr(temp1, pending_address_src_);
32 __ Ldr(temp2, src_operand);
35 __ Ldp(temp1, temp2, pending_address_src_);
38 __ Ldp(temp2, temp1, src_operand);
44 __ Str(temp1, pending_address_dst_);
45 __ Str(temp2, dst_operand);
48 __ Stp(temp1, temp2, pending_address_dst_);
51 __ Stp(temp2, temp1, dst_operand);
59 pending_ = kStackSlotMove;
60 pending_address_src_ = src_operand;
61 pending_address_dst_ = dst_operand;
63 pending_pc_ = masm_->pc_offset();
68 void DelayedMasm::StoreConstant(uint64_t value,
const MemOperand& operand) {
69 DCHECK(!scratch_register_acquired_);
70 if ((pending_ == kStoreConstant) && (value == pending_value_)) {
76 pending_address_dst_ :
78 DCHECK(pending_pc_ == masm_->pc_offset());
79 if (pending_value_ == 0) {
80 __ Stp(xzr, xzr, dst);
82 SetSavedValue(pending_value_);
83 __ Stp(ScratchRegister(), ScratchRegister(), dst);
91 pending_ = kStoreConstant;
92 pending_address_dst_ = operand;
93 pending_value_ = value;
95 pending_pc_ = masm_->pc_offset();
100 void DelayedMasm::Load(
const CPURegister& rd,
const MemOperand& operand) {
101 if ((pending_ == kLoad) &&
102 pending_register_.IsSameSizeAndType(rd)) {
107 DCHECK(pending_pc_ == masm_->pc_offset());
108 DCHECK(!IsScratchRegister(pending_register_) ||
109 scratch_register_acquired_);
110 DCHECK(!IsScratchRegister(rd) || scratch_register_acquired_);
111 __ Ldp(pending_register_, rd, pending_address_src_);
115 DCHECK(pending_pc_ == masm_->pc_offset());
116 DCHECK(!IsScratchRegister(pending_register_) ||
117 scratch_register_acquired_);
118 DCHECK(!IsScratchRegister(rd) || scratch_register_acquired_);
119 __ Ldp(rd, pending_register_, operand);
127 pending_register_ = rd;
128 pending_address_src_ = operand;
130 pending_pc_ = masm_->pc_offset();
135 void DelayedMasm::Store(
const CPURegister& rd,
const MemOperand& operand) {
136 if ((pending_ == kStore) &&
137 pending_register_.IsSameSizeAndType(rd)) {
142 DCHECK(pending_pc_ == masm_->pc_offset());
143 __ Stp(pending_register_, rd, pending_address_dst_);
147 DCHECK(pending_pc_ == masm_->pc_offset());
148 __ Stp(rd, pending_register_, operand);
156 pending_register_ = rd;
157 pending_address_dst_ = operand;
159 pending_pc_ = masm_->pc_offset();
164 void DelayedMasm::EmitPending() {
165 DCHECK((pending_ == kNone) || (pending_pc_ == masm_->pc_offset()));
170 if (pending_value_ == 0) {
171 __ Str(xzr, pending_address_dst_);
173 SetSavedValue(pending_value_);
174 __ Str(ScratchRegister(), pending_address_dst_);
178 DCHECK(!IsScratchRegister(pending_register_) ||
179 scratch_register_acquired_);
180 __ Ldr(pending_register_, pending_address_src_);
183 __ Str(pending_register_, pending_address_dst_);
185 case kStackSlotMove: {
186 UseScratchRegisterScope scope(masm_);
188 __ Ldr(temp, pending_address_src_);
189 __ Str(temp, pending_address_dst_);
static PairResult AreConsistentForPair(const MemOperand &operandA, const MemOperand &operandB, int access_size_log2=kXRegSizeLog2)
#define DCHECK(condition)
DwVfpRegister DoubleRegister
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