5 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
6 #define V8_ARM64_ASSEMBLER_ARM64_H_
25 #define REGISTER_CODE_LIST(R) \
26 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \
27 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \
28 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \
29 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
56 unsigned code()
const;
191 const char*
const names[] = {
192 "x0",
"x1",
"x2",
"x3",
"x4",
193 "x5",
"x6",
"x7",
"x8",
"x9",
194 "x10",
"x11",
"x12",
"x13",
"x14",
195 "x15",
"x18",
"x19",
"x20",
"x21",
196 "x22",
"x23",
"x24",
"x27",
303 const char*
const names[] = {
304 "d0",
"d1",
"d2",
"d3",
"d4",
"d5",
"d6",
"d7",
305 "d8",
"d9",
"d10",
"d11",
"d12",
"d13",
"d14",
306 "d16",
"d17",
"d18",
"d19",
"d20",
"d21",
"d22",
"d23",
307 "d24",
"d25",
"d26",
"d27",
"d28"
333 #if defined(ARM64_DEFINE_REG_STATICS)
334 #define INITIALIZE_REGISTER(register_class, name, code, size, type) \
335 const CPURegister init_##register_class##_##name = {code, size, type}; \
336 const register_class& name = *reinterpret_cast<const register_class*>( \
337 &init_##register_class##_##name)
338 #define ALIAS_REGISTER(register_class, alias, name) \
339 const register_class& alias = *reinterpret_cast<const register_class*>( \
340 &init_##register_class##_##name)
342 #define INITIALIZE_REGISTER(register_class, name, code, size, type) \
343 extern const register_class& name
344 #define ALIAS_REGISTER(register_class, alias, name) \
345 extern const register_class& alias
358 #define DEFINE_REGISTERS(N) \
359 INITIALIZE_REGISTER(Register, w##N, N, \
360 kWRegSizeInBits, CPURegister::kRegister); \
361 INITIALIZE_REGISTER(Register, x##N, N, \
362 kXRegSizeInBits, CPURegister::kRegister);
364 #undef DEFINE_REGISTERS
371 #define DEFINE_FPREGISTERS(N) \
372 INITIALIZE_REGISTER(FPRegister, s##N, N, \
373 kSRegSizeInBits, CPURegister::kFPRegister); \
374 INITIALIZE_REGISTER(FPRegister, d##N, N, \
375 kDRegSizeInBits, CPURegister::kFPRegister);
377 #undef DEFINE_FPREGISTERS
379 #undef INITIALIZE_REGISTER
412 #undef ALIAS_REGISTER
457 :
list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
469 unsigned first_reg,
unsigned last_reg)
475 DCHECK(last_reg >= first_reg);
476 list_ = (1UL << (last_reg + 1)) - 1;
477 list_ &= ~((1UL << first_reg) - 1);
548 if (!other2.IsNone() && (other2.type() ==
type_))
list |= other2.Bit();
549 if (!other3.IsNone() && (other3.type() ==
type_))
list |= other3.Bit();
550 if (!other4.IsNone() && (other4.type() ==
type_))
list |= other4.Bit();
581 const RegList kValidRegisters = 0x8000000ffffffff;
582 const RegList kValidFPRegisters = 0x0000000ffffffff;
599 #define kCalleeSaved CPURegList::GetCalleeSaved()
600 #define kCalleeSavedFP CPURegList::GetCalleeSavedFP()
604 #define kCallerSaved CPURegList::GetCallerSaved()
605 #define kCallerSavedFP CPURegList::GetCallerSavedFP()
673 inline bool IsZero()
const;
930 DCHECK(label->is_bound());
1052 void b(Label* label);
1237 bfm(rd, rn, lsb, lsb + width - 1);
1264 sbfm(rd, rn, lsb, lsb + width - 1);
1274 sbfm(rd, rn, 0, 15);
1279 sbfm(rd, rn, 0, 31);
1287 ubfm(rd, rn, (reg_size -
shift) % reg_size, reg_size -
shift - 1);
1313 ubfm(rd, rn, lsb, lsb + width - 1);
1323 ubfm(rd, rn, 0, 15);
1328 ubfm(rd, rn, 0, 31);
1763 return reinterpret_cast<byte*
>(instr) -
buffer_;
1769 return rd.
code() << Rd_offset;
1774 return rn.
code() << Rn_offset;
1779 return rm.
code() << Rm_offset;
1784 return ra.
code() << Ra_offset;
1789 return rt.
code() << Rt_offset;
1794 return rt2.
code() << Rt2_offset;
1826 inline static Instr ImmS(
unsigned imms,
unsigned reg_size);
1827 inline static Instr ImmR(
unsigned immr,
unsigned reg_size);
1831 inline static Instr BitN(
unsigned bitn,
unsigned reg_size);
1982 unsigned left_shift);
2092 memcpy(
pc_, &instruction,
sizeof(instruction));
2093 pc_ +=
sizeof(instruction);
2187 static const int kGap = 128;
2265 reinterpret_cast<
byte*>(start),
#define DEFINE_FPREGISTERS(N)
#define REGISTER_CODE_LIST(R)
#define DEFINE_REGISTERS(N)
Isolate * isolate() const
DISALLOW_IMPLICIT_CONSTRUCTORS(BlockConstPoolScope)
BlockConstPoolScope(Assembler *assem)
BlockPoolsScope(Assembler *assem)
DISALLOW_IMPLICIT_CONSTRUCTORS(BlockPoolsScope)
FarBranchInfo(int offset, Label *label)
static const int kSpecialTargetSize
static Instr Flags(FlagsUpdate S)
void uxtb(const Register &rd, const Register &rn)
void LogicalImmediate(const Register &rd, const Register &rn, unsigned n, unsigned imm_s, unsigned imm_r, LogicalOp op)
void fabs(const FPRegister &fd, const FPRegister &fn)
void sbcs(const Register &rd, const Register &rn, const Operand &operand)
static Instr SF(Register rd)
void rev32(const Register &rd, const Register &rn)
static Instr RnSP(Register rn)
RelocInfoWriter reloc_info_writer
void RecordLiteral(int64_t imm, unsigned size)
static Instr ImmR(unsigned immr, unsigned reg_size)
void cset(const Register &rd, Condition cond)
void umaddl(const Register &rd, const Register &rn, const Register &rm, const Register &ra)
static Instr ImmTestBranch(int imm14)
void fcvtms(const Register &rd, const FPRegister &fn)
void mul(const Register &rd, const Register &rn, const Register &rm)
void fmov(FPRegister fd, double imm)
static Instr RdSP(Register rd)
int next_constant_pool_check_
bool IsConstPoolEmpty() const
static Instr ImmCondCmp(unsigned imm)
void fmov(FPRegister fd, float imm)
static const int kMaxRelocSize
static const int kCheckConstPoolInterval
void fcvtmu(const Register &rd, const FPRegister &fn)
void csetm(const Register &rd, Condition cond)
static Instr ImmMoveWide(uint64_t imm)
static Instr ImmFP32(float imm)
void DataProcExtendedRegister(const Register &rd, const Register &rn, const Operand &operand, FlagsUpdate S, Instr op)
int next_veneer_pool_check_
void ngcs(const Register &rd, const Operand &operand)
void rbit(const Register &rd, const Register &rn)
void frintn(const FPRegister &fd, const FPRegister &fn)
void movn(const Register &rd, uint64_t imm, int shift=-1)
static Instr ImmCmpBranch(int imm19)
static Instr Nzcv(StatusFlags nzcv)
static Instr ImmLSPair(int imm7, LSDataSize size)
void hint(SystemHint code)
static Instr Ra(CPURegister ra)
void RecordConstPool(int size)
void fnmsub(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, const FPRegister &fa)
static Address target_address_at(Address pc, ConstantPoolArray *constant_pool)
void eor(const Register &rd, const Register &rn, const Operand &operand)
void smull(const Register &rd, const Register &rn, const Register &rm)
void ConditionalSelect(const Register &rd, const Register &rn, const Register &rm, Condition cond, ConditionalSelectOp op)
void fminnm(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
static const int kVeneerDistanceCheckMargin
static Instr ImmPCRelAddress(int imm21)
static Instr ImmException(int imm16)
void stnp(const CPURegister &rt, const CPURegister &rt2, const MemOperand &dst)
void ands(const Register &rd, const Register &rn, const Operand &operand)
void csinc(const Register &rd, const Register &rn, const Register &rm, Condition cond)
void adcs(const Register &rd, const Register &rn, const Operand &operand)
void AddSubWithCarry(const Register &rd, const Register &rn, const Operand &operand, FlagsUpdate S, AddSubWithCarryOp op)
void fmov(FPRegister fd, FPRegister fn)
void br(const Register &xn)
static LoadStoreOp StoreOpFor(const CPURegister &rt)
void DeleteUnresolvedBranchInfoForLabelTraverse(Label *label)
void str(const CPURegister &rt, const MemOperand &dst)
void cmn(const Register &rn, const Operand &operand)
TypeFeedbackId RecordedAstId()
void fcmp(const FPRegister &fn, const FPRegister &fm)
void extr(const Register &rd, const Register &rn, const Register &rm, unsigned lsb)
uint64_t SizeOfCodeGeneratedSince(const Label *label)
void RecordVeneerPool(int location_offset, int size)
void ubfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
static bool IsConstantPoolAt(Instruction *instr)
void fcvtzu(const Register &rd, const FPRegister &fn)
static Instr Cond(Condition cond)
void strh(const Register &rt, const MemOperand &dst)
static Instr Rm(CPURegister rm)
static Instr Rd(CPURegister rd)
void sxtw(const Register &rd, const Register &rn)
void fmax(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
void mneg(const Register &rd, const Register &rn, const Register &rm)
void mvn(const Register &rd, const Operand &operand)
static Instr ImmExtendShift(unsigned left_shift)
uint64_t SizeOfGeneratedCode() const
void bfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
void ccmn(const Register &rn, const Operand &operand, StatusFlags nzcv, Condition cond)
void ClearRecordedAstId()
void udiv(const Register &rd, const Register &rn, const Register &rm)
TypeFeedbackId recorded_ast_id_
void DataProcessing3Source(const Register &rd, const Register &rn, const Register &rm, const Register &ra, DataProcessing3SourceOp op)
static LoadStorePairNonTemporalOp LoadPairNonTemporalOpFor(const CPURegister &rt, const CPURegister &rt2)
static const int kVeneerDistanceMargin
void subs(const Register &rd, const Register &rn, const Operand &operand)
void EndBlockVeneerPool()
void uxth(const Register &rd, const Register &rn)
void asrv(const Register &rd, const Register &rn, const Register &rm)
static const int kDebugBreakSlotInstructions
void GetCode(CodeDesc *desc)
void ldr_pcrel(const CPURegister &rt, int imm19)
void bfi(const Register &rd, const Register &rn, unsigned lsb, unsigned width)
void ror(const Register &rd, const Register &rs, unsigned shift)
void fcvtnu(const Register &rd, const FPRegister &fn)
void CheckConstPool(bool force_emit, bool require_jump)
static const int kPatchDebugBreakSlotAddressOffset
void ngc(const Register &rd, const Operand &operand)
void madd(const Register &rd, const Register &rn, const Register &rm, const Register &ra)
ptrdiff_t InstructionOffset(Instruction *instr) const
static LoadLiteralOp LoadLiteralOpFor(const CPURegister &rt)
void b(Label *label, Condition cond)
static Instr ShiftMoveWide(int64_t shift)
static Instr ImmLLiteral(int imm19)
void sxth(const Register &rd, const Register &rn)
void StartBlockConstPool()
void neg(const Register &rd, const Operand &operand)
void AssertSizeOfCodeGeneratedSince(const Label *label, ptrdiff_t size)
void tbz(const Register &rt, unsigned bit_pos, Label *label)
void ldrsw(const Register &rt, const MemOperand &src)
static LoadStorePairOp LoadPairOpFor(const CPURegister &rt, const CPURegister &rt2)
void ubfx(const Register &rd, const Register &rn, unsigned lsb, unsigned width)
static Instr Rt(CPURegister rt)
static const int kStartOfLabelLinkChain
void frinta(const FPRegister &fd, const FPRegister &fn)
void fdiv(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
void fcvtzs(const Register &rd, const FPRegister &fn)
static Instr ImmShiftLS(unsigned shift_amount)
static const int kPatchDebugBreakSlotReturnOffset
void StartBlockVeneerPool()
static Instr ImmSystemRegister(int imm15)
void BlockConstPoolFor(int instructions)
void lslv(const Register &rd, const Register &rn, const Register &rm)
void cmp(const Register &rn, const Operand &operand)
void mov(const Register &rd, const Register &rn)
static Instr ImmLS(int imm9)
static Address break_address_from_return_address(Address pc)
void EmitExtendShift(const Register &rd, const Register &rn, Extend extend, unsigned left_shift)
void lsr(const Register &rd, const Register &rn, unsigned shift)
void strb(const Register &rt, const MemOperand &dst)
static Instr ImmSetBits(unsigned imms, unsigned reg_size)
void msr(SystemRegister sysreg, const Register &rt)
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data=0)
static bool IsImmAddSub(int64_t immediate)
static Instr ImmDPShift(unsigned amount)
void shift(Register dst, Immediate shift_amount, int subcode, int size)
Assembler(Isolate *arg_isolate, void *buffer, int buffer_size)
void fadd(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
void msub(const Register &rd, const Register &rn, const Register &rm, const Register &ra)
void fmin(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
void cneg(const Register &rd, const Register &rn, Condition cond)
void dsb(BarrierDomain domain, BarrierType type)
void DeleteUnresolvedBranchInfoForLabel(Label *label)
void adc(const Register &rd, const Register &rn, const Operand &operand)
static Instr ImmFP64(double imm)
void DataProcShiftedRegister(const Register &rd, const Register &rn, const Operand &operand, FlagsUpdate S, Instr op)
void add(const Register &rd, const Register &rn, const Operand &operand)
void ldrb(const Register &rt, const MemOperand &src)
static Instr FPType(FPRegister fd)
void ldrsb(const Register &rt, const MemOperand &src)
void fcvtns(const Register &rd, const FPRegister &fn)
void dmb(BarrierDomain domain, BarrierType type)
void fcsel(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, Condition cond)
void cls(const Register &rd, const Register &rn)
bool ShouldEmitVeneers(int margin=kVeneerDistanceMargin)
void fmov(FPRegister fd, Register rn)
static const int kApproxMaxPoolEntryCount
void sbfm(const Register &rd, const Register &rn, unsigned immr, unsigned imms)
static Instr Rt2(CPURegister rt2)
void rorv(const Register &rd, const Register &rn, const Register &rm)
void fsqrt(const FPRegister &fd, const FPRegister &fn)
static Instr ImmBarrierType(int imm2)
void ConditionalCompare(const Register &rn, const Operand &operand, StatusFlags nzcv, Condition cond, ConditionalCompareOp op)
void smaddl(const Register &rd, const Register &rn, const Register &rm, const Register &ra)
static bool IsImmLSScaled(int64_t offset, LSDataSize size)
void RemoveBranchFromLabelLinkChain(Instruction *branch, Label *label, Instruction *label_veneer=NULL)
void Emit(Instr instruction)
void fmaxnm(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
int InstructionsGeneratedSince(const Label *label)
void scvtf(const FPRegister &fd, const Register &rn, unsigned fbits=0)
Handle< ConstantPoolArray > NewConstantPool(Isolate *isolate)
int unresolved_branches_first_limit() const
static const int kCallSizeWithoutRelocation
void ldp(const CPURegister &rt, const CPURegister &rt2, const MemOperand &src)
static Instr ExtendMode(Extend extend)
void smsubl(const Register &rd, const Register &rn, const Register &rm, const Register &ra)
static bool IsImmLSPair(int64_t offset, LSDataSize size)
int const_pool_blocked_nesting_
void LoadStore(const CPURegister &rt, const MemOperand &addr, LoadStoreOp op)
void EmitVeneers(bool force_emit, bool need_protection, int margin=kVeneerDistanceMargin)
void fneg(const FPRegister &fd, const FPRegister &fn)
void RecordComment(const char *msg)
void FPDataProcessing3Source(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, const FPRegister &fa, FPDataProcessing3SourceOp op)
int LinkAndGetByteOffsetTo(Label *label)
void frintz(const FPRegister &fd, const FPRegister &fn)
void adr(const Register &rd, Label *label)
friend class PositionsRecorder
void adr(const Register &rd, int imm21)
static Instr ImmS(unsigned imms, unsigned reg_size)
static Instr ImmRotate(unsigned immr, unsigned reg_size)
static Instr ShiftDP(Shift shift)
void FPConvertToInt(const Register &rd, const FPRegister &fn, FPIntegerConvertOp op)
static LSDataSize CalcLSDataSize(LoadStoreOp op)
void orr(const Register &rd, const Register &rn, const Operand &operand)
static const int kMaxVeneerCodeSize
bool is_const_pool_blocked() const
void lsl(const Register &rd, const Register &rn, unsigned shift)
void cinc(const Register &rd, const Register &rn, Condition cond)
static Address target_pointer_address_at(Address pc)
int veneer_pool_blocked_nesting_
void smulh(const Register &rd, const Register &rn, const Register &rm)
void fmul(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
void sub(const Register &rd, const Register &rn, const Operand &operand)
void mov(Register dst, const Operand &src, SBit s=LeaveCC, Condition cond=al)
void csel(const Register &rd, const Register &rn, const Register &rm, Condition cond)
static void set_target_address_at(Address pc, ConstantPoolArray *constant_pool, Address target, ICacheFlushMode icache_flush_mode=FLUSH_ICACHE_IF_NEEDED)
void fnmadd(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, const FPRegister &fa)
static Address target_address_from_return_address(Address pc)
void tst(const Register &rn, const Operand &operand)
void SetRecordedAstId(TypeFeedbackId ast_id)
void ldrsh(const Register &rt, const MemOperand &src)
void ldnp(const CPURegister &rt, const CPURegister &rt2, const MemOperand &src)
void tbz(const Register &rt, unsigned bit_pos, int imm14)
void bics(const Register &rd, const Register &rn, const Operand &operand)
static Instr ImmCondBranch(int imm19)
void and_(const Register &rd, const Register &rn, const Operand &operand)
void ucvtf(const FPRegister &fd, const Register &rn, unsigned fbits=0)
void ldr(const CPURegister &rt, const Immediate &imm)
void eon(const Register &rd, const Register &rn, const Operand &operand)
static LoadStorePairNonTemporalOp StorePairNonTemporalOpFor(const CPURegister &rt, const CPURegister &rt2)
void movz(const Register &rd, uint64_t imm, int shift=-1)
static Instr BitN(unsigned bitn, unsigned reg_size)
void b(int imm19, Condition cond)
void cbnz(const Register &rt, int imm19)
void RecordDebugBreakSlot()
void tbnz(const Register &rt, unsigned bit_pos, Label *label)
static Address return_address_from_call_start(Address pc)
void ccmp(const Register &rn, const Operand &operand, StatusFlags nzcv, Condition cond)
void rev16(const Register &rd, const Register &rn)
void bfxil(const Register &rd, const Register &rn, unsigned lsb, unsigned width)
void MoveWide(const Register &rd, uint64_t imm, int shift, MoveWideImmediateOp mov_op)
void fcvt(const FPRegister &fd, const FPRegister &fn)
void EmitShift(const Register &rd, const Register &rn, Shift shift, unsigned amount)
static const int kDebugBreakSlotLength
static Instr ImmHint(int imm7)
static LoadStorePairOp StorePairOpFor(const CPURegister &rt, const CPURegister &rt2)
void adds(const Register &rd, const Register &rn, const Operand &operand)
void LoadStorePairNonTemporal(const CPURegister &rt, const CPURegister &rt2, const MemOperand &addr, LoadStorePairNonTemporalOp op)
void sbfiz(const Register &rd, const Register &rn, unsigned lsb, unsigned width)
void movk(const Register &rd, uint64_t imm, int shift=-1)
void frintm(const FPRegister &fd, const FPRegister &fn)
int LinkAndGetInstructionOffsetTo(Label *label)
static Instr Rn(CPURegister rn)
void orn(const Register &rd, const Register &rn, const Operand &operand)
void CheckVeneerPool(bool force_emit, bool require_jump, int margin=kVeneerDistanceMargin)
void bic(const Register &rd, const Register &rn, const Operand &operand)
void cinv(const Register &rd, const Register &rn, Condition cond)
static void deserialization_set_special_target_at(Address constant_pool_entry, Code *code, Address target)
void EmitStringData(const char *string)
void fcvtau(const Register &rd, const FPRegister &fn)
STATIC_ASSERT(kPointerSize==kInt64Size||kPointerSize==kInt32Size)
int no_const_pool_before_
std::multimap< int, FarBranchInfo > unresolved_branches_
void blr(const Register &xn)
virtual void AbortedCodeGeneration()
static const int kJSRetSequenceInstructions
static LoadStoreOp LoadOpFor(const CPURegister &rt)
void fsub(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm)
void SetNextConstPoolCheckIn(int instructions)
Instruction * InstructionAt(int offset) const
static const int kPatchReturnSequenceAddressOffset
void nop(NopMarkerTypes n)
void tbnz(const Register &rt, unsigned bit_pos, int imm14)
void fmadd(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, const FPRegister &fa)
void DataProcessing1Source(const Register &rd, const Register &rn, DataProcessing1SourceOp op)
void LoadStorePair(const CPURegister &rt, const CPURegister &rt2, const MemOperand &addr, LoadStorePairOp op)
void stp(const CPURegister &rt, const CPURegister &rt2, const MemOperand &dst)
void fcmp(const FPRegister &fn, double value)
static Instr FPScale(unsigned scale)
static const int kVeneerNoProtectionFactor
void negs(const Register &rd, const Operand &operand)
void fcvtas(const Register &rd, const FPRegister &fn)
static Instr ImmUncondBranch(int imm26)
void cbnz(const Register &rt, Label *label)
static Instr ImmAddSub(int64_t imm)
void AddSub(const Register &rd, const Register &rn, const Operand &operand, FlagsUpdate S, AddSubOp op)
void cbz(const Register &rt, int imm19)
static bool IsImmLogical(uint64_t value, unsigned width, unsigned *n, unsigned *imm_s, unsigned *imm_r)
static bool IsImmFP64(double imm)
void cbz(const Register &rt, Label *label)
void fmsub(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, const FPRegister &fa)
void CheckLabelLinkChain(Label const *label)
void uxtw(const Register &rd, const Register &rn)
void fccmp(const FPRegister &fn, const FPRegister &fm, StatusFlags nzcv, Condition cond)
PositionsRecorder positions_recorder_
void fmov(Register rd, FPRegister fn)
void clz(const Register &rd, const Register &rn)
PositionsRecorder * positions_recorder()
void sdiv(const Register &rd, const Register &rn, const Register &rm)
void mrs(const Register &rt, SystemRegister sysreg)
static Instr ImmLSUnsigned(int imm12)
void EmitData(void const *data, unsigned size)
static const int kCallSizeWithRelocation
void sxtb(const Register &rd, const Register &rn)
void debug(const char *message, uint32_t code, Instr params=BREAK)
void ubfiz(const Register &rd, const Register &rn, unsigned lsb, unsigned width)
void rev(const Register &rd, const Register &rn)
int SizeOfCodeGeneratedSince(Label *label)
void ret(const Register &xn=lr)
void asr(const Register &rd, const Register &rn, unsigned shift)
void umsubl(const Register &rd, const Register &rn, const Register &rm, const Register &ra)
void sbc(const Register &rd, const Register &rn, const Operand &operand)
void FPDataProcessing2Source(const FPRegister &fd, const FPRegister &fn, const FPRegister &fm, FPDataProcessing2SourceOp op)
void Logical(const Register &rd, const Register &rn, const Operand &operand, LogicalOp op)
static bool IsImmConditionalCompare(int64_t immediate)
bool is_veneer_pool_blocked() const
static bool IsImmFP32(float imm)
static Instr ImmTestBranchBit(unsigned bit_pos)
void ldrh(const Register &rt, const MemOperand &src)
static Instr ImmBarrierDomain(int imm2)
void ldr(const CPURegister &rt, const MemOperand &src)
void FPDataProcessing1Source(const FPRegister &fd, const FPRegister &fn, FPDataProcessing1SourceOp op)
const Register & AppropriateZeroRegFor(const CPURegister ®) const
static const int kApproxMaxDistToConstPool
static int ConstantPoolSizeAt(Instruction *instr)
void PopulateConstantPool(ConstantPoolArray *constant_pool)
void csinv(const Register &rd, const Register &rn, const Register &rm, Condition cond)
static bool IsImmLSUnscaled(int64_t offset)
void csneg(const Register &rd, const Register &rn, const Register &rm, Condition cond)
bool ShouldEmitVeneer(int max_reachable_pc, int margin=kVeneerDistanceMargin)
void lsrv(const Register &rd, const Register &rn, const Register &rm)
void sbfx(const Register &rd, const Register &rn, unsigned lsb, unsigned width)
void ldpsw(const Register &rt, const Register &rt2, const MemOperand &src)
EnsureSpace(Assembler *assembler)
static CPURegList GetCallerSavedFP(unsigned size=kDRegSizeInBits)
void Remove(const CPURegList &other)
static CPURegList GetCallerSaved(unsigned size=kXRegSizeInBits)
bool IncludesAliasOf(const CPURegister &other1, const CPURegister &other2=NoCPUReg, const CPURegister &other3=NoCPUReg, const CPURegister &other4=NoCPUReg) const
static CPURegList GetSafepointSavedRegisters()
CPURegister PopHighestIndex()
CPURegister::RegisterType type() const
unsigned RegisterSizeInBits() const
CPURegList(CPURegister::RegisterType type, unsigned size, unsigned first_reg, unsigned last_reg)
CPURegister::RegisterType type_
CPURegList(CPURegister::RegisterType type, unsigned size, RegList list)
unsigned RegisterSizeInBytes() const
CPURegister PopLowestIndex()
static CPURegList GetCalleeSaved(unsigned size=kXRegSizeInBits)
unsigned TotalSizeInBytes() const
static CPURegList GetCalleeSavedFP(unsigned size=kDRegSizeInBits)
void Combine(const CPURegList &other)
void set_list(RegList new_list)
CPURegList(CPURegister reg1, CPURegister reg2=NoCPUReg, CPURegister reg3=NoCPUReg, CPURegister reg4=NoCPUReg)
ConstPool(Assembler *assm)
std::multimap< uint64_t, int > shared_entries_
void RecordEntry(intptr_t data, RelocInfo::Mode mode)
int SizeIfEmittedAtCurrentPc(bool require_jump)
void Emit(bool require_jump)
std::vector< std::pair< uint64_t, int > > unique_entries_
bool CanBeShared(RelocInfo::Mode mode)
static void FlushICache(void *start, size_t size)
static Instruction * Cast(T src)
const Register & regoffset() const
Operand OffsetAsOperand() const
bool IsImmediateOffset() const
AddrMode addrmode() const
const Register & base() const
bool IsRegisterOffset() const
unsigned shift_amount() const
static PairResult AreConsistentForPair(const MemOperand &operandA, const MemOperand &operandB, int access_size_log2=kXRegSizeLog2)
Operand(Register reg, Shift shift=LSL, unsigned shift_amount=0)
bool IsExtendedRegister() const
int64_t ImmediateValue() const
unsigned shift_amount() const
bool NeedsRelocation(const Assembler *assembler) const
static Operand UntagSmiAndScale(Register smi, int scale)
static Operand UntagSmi(Register smi)
Operand ToExtendedRegister() const
bool IsShiftedRegister() const
Immediate immediate() const
static const int kAdrFarPatchableNNops
PatchingAssembler(Instruction *start, unsigned count)
static const int kAdrFarPatchableNInstrs
PatchingAssembler(byte *start, unsigned count)
void PatchAdrFar(int64_t target_offset)
enable harmony numeric enable harmony object literal extensions Optimize object size
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
bool AreSameSizeAndType(const CPURegister ®1, const CPURegister ®2, const CPURegister ®3=NoCPUReg, const CPURegister ®4=NoCPUReg, const CPURegister ®5=NoCPUReg, const CPURegister ®6=NoCPUReg, const CPURegister ®7=NoCPUReg, const CPURegister ®8=NoCPUReg)
static const int kRegListSizeInBits
FPDataProcessing2SourceOp
const unsigned kDRegSizeInBits
bool AreAliased(const CPURegister ®1, const CPURegister ®2, const CPURegister ®3=NoReg, const CPURegister ®4=NoReg, const CPURegister ®5=NoReg, const CPURegister ®6=NoReg, const CPURegister ®7=NoReg, const CPURegister ®8=NoReg)
const unsigned kXRegSizeInBits
LoadStorePairNonTemporalOp
const unsigned kSPRegInternalCode
DwVfpRegister DoubleRegister
Register GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2=NoReg, Register reg3=NoReg, Register reg4=NoReg)
const unsigned kWRegSizeInBits
FPDataProcessing3SourceOp
FPDataProcessing1SourceOp
Handle< T > handle(T *t, Isolate *isolate)
const unsigned kNumberOfFPRegisters
const unsigned kRegCodeMask
INITIALIZE_REGISTER(Register, NoReg, 0, 0, CPURegister::kNoRegister)
const uint64_t kSmiShiftMask
const unsigned kXRegSizeLog2
STATIC_ASSERT(sizeof(CPURegister)==sizeof(Register))
int CountSetBits(uint64_t value, int width)
const unsigned kNumberOfRegisters
const unsigned kInstructionSize
const LowDwVfpRegister d15
ALIAS_REGISTER(Register, ip0, x16)
Debugger support for the V8 JavaScript engine.
bool Aliases(const CPURegister &other) const
RegisterType type() const
bool IsValidFPRegister() const
bool Is(const CPURegister &other) const
static CPURegister Create(unsigned code, unsigned size, RegisterType type)
bool IsFPRegister() const
unsigned SizeInBits() const
bool IsValidOrNone() const
bool IsValidRegister() const
bool IsSameSizeAndType(const CPURegister &other) const
bool is(const CPURegister &other) const
static const unsigned kAllocatableHighRangeBegin
static const unsigned kAllocatableHighRangeEnd
static FPRegister SRegFromCode(unsigned code)
static const int kAllocatableRangeGapSize
static FPRegister from_code(int code)
static const int kMaxNumRegisters
FPRegister(const FPRegister &r)
static const unsigned kAllocatableLowRangeBegin
static const char * AllocationIndexToString(int index)
static int NumAllocatableRegisters()
static const int kMaxNumAllocatableRegisters
static FPRegister Create(unsigned code, unsigned size)
bool IsAllocatable() const
static const unsigned kAllocatableLowRangeEnd
static FPRegister DRegFromCode(unsigned code)
static const RegList kAllocatableFPRegisters
static int NumAllocatableAliasedRegisters()
static int ToAllocationIndex(FPRegister reg)
FPRegister(const CPURegister &r)
static FPRegister FromAllocationIndex(unsigned int index)
static const int kNumRegisters
static const int kAllocatableRangeGapSize
static int NumRegisters()
static int NumAllocatableRegisters()
static const unsigned kAllocatableHighRangeBegin
static const unsigned kAllocatableLowRangeEnd
static const unsigned kAllocatableHighRangeEnd
bool IsAllocatable() const
static Register WRegFromCode(unsigned code)
static Register from_code(int code)
static int ToAllocationIndex(Register reg)
Register(const Register &r)
static Register XRegFromCode(unsigned code)
static const char * AllocationIndexToString(int index)
static int NumAllocatableRegisters()
static Register Create(unsigned code, unsigned size)
static Register FromAllocationIndex(unsigned index)
static const int kMaxNumAllocatableRegisters
static const unsigned kAllocatableContext
static const unsigned kAllocatableLowRangeBegin
Register(const CPURegister &r)
#define T(name, string, precedence)