5 #ifndef V8_HYDROGEN_FLOW_ENGINE_H_
6 #define V8_HYDROGEN_FLOW_ENGINE_H_
23 template <
class State>
67 template <
class State,
class Effects>
74 pred_counts_(graph->blocks()->length(), zone),
84 for (HInstructionIterator it(block); !it.Done(); it.Advance()) {
97 for (
int i = root->block_id(); i < graph_->blocks()->length();
i++) {
98 HBasicBlock* block =
graph_->blocks()->at(
i);
104 if (block->IsReachable()) {
106 if (block->IsLoopHeader()) {
115 for (HInstructionIterator it(block); !it.Done(); it.Advance()) {
121 int max = block->end()->SuccessorCount();
122 for (
int i = 0;
i < max;
i++) {
123 HBasicBlock* succ = block->end()->SuccessorAt(
i);
126 if (max == 1 && succ->predecessors()->length() == 1) {
142 DCHECK(block->IsLoopHeader());
144 if (effects !=
NULL)
return effects;
148 if (effects->
Disabled())
return effects;
150 HLoopInformation* loop = block->loop_information();
151 int end = loop->GetLastBackEdge()->block_id();
153 for (
int i = block->block_id();
i <= end;
i++) {
154 HBasicBlock* member =
graph_->blocks()->at(
i);
155 if (
i != block->block_id() && member->IsLoopHeader()) {
157 DCHECK(member->loop_information()->parent_loop() == loop);
161 i = member->loop_information()->GetLastBackEdge()->block_id();
164 if (member->IsUnreachable())
continue;
165 DCHECK(member->current_loop() == loop);
166 for (HInstructionIterator it(member); !it.Done(); it.Advance()) {
175 if (root->block_id() == 0)
return false;
176 if (root == other)
return false;
177 return !root->Dominates(other);
190 pred_counts_.Rewind(0);
191 pred_counts_.AddBlock(0,
graph_->blocks()->length(),
zone_);
198 DCHECK(block->predecessors()->length() == pred_counts_[block->block_id()]);
203 pred_counts_[block->block_id()]++;
void Union(Effects *that, Zone *zone)
void Process(HInstruction *instr, Zone *zone)
State * AnalyzeOneBlock(HBasicBlock *block, State *state)
ZoneList< Effects * > loop_effects_
State * StateAt(HBasicBlock *block)
void SetStateAt(HBasicBlock *block, State *state)
HFlowEngine(HGraph *graph, Zone *zone)
void AnalyzeDominatedBlocks(HBasicBlock *root, State *initial)
Effects * ComputeLoopEffects(HBasicBlock *block)
bool SkipNonDominatedBlock(HBasicBlock *root, HBasicBlock *other)
ZoneList< State * > block_states_
void CheckPredecessorCount(HBasicBlock *block)
void IncrementPredecessorCount(HBasicBlock *block)
void Process(HInstruction *value, Zone *zone)
void Union(NoEffects *other, Zone *zone)
NoState * Merge(HBasicBlock *succ, NoState *other, Zone *zone)
NoState * Process(HInstruction *value, Zone *zone)
NoState * Copy(HBasicBlock *succ, Zone *zone)
static State * Finish(State *state, HBasicBlock *block, Zone *zone)
State * Process(HInstruction *instr, Zone *zone)
static State * Merge(State *succ_state, HBasicBlock *succ_block, State *pred_state, HBasicBlock *pred_block, Zone *zone)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
Debugger support for the V8 JavaScript engine.