43 return result + delta;
52 if (!FLAG_enable_ool_constant_pool) {
76 if (FLAG_enable_ool_constant_pool) {
104 if (old_target->
kind() == Code::STORE_IC ||
105 old_target->
kind() == Code::KEYED_STORE_IC) {
111 target->instruction_start());
123 code->VerifyEmbeddedObjectsDependency();
161 template <
class TypeClass>
163 if (type->Is(TypeClass::Boolean())) {
164 return native_context->boolean_function();
165 }
else if (type->Is(TypeClass::Number())) {
166 return native_context->number_function();
167 }
else if (type->Is(TypeClass::String())) {
168 return native_context->string_function();
170 return native_context->symbol_function();
180 if (receiver_is_holder) {
186 if (builtin_ctor !=
NULL) {
190 *
flag = receiver_map->is_dictionary_map()
194 return handle(JSObject::cast(receiver_map->prototype())->map());
202 if (builtin_ctor !=
NULL) {
214 Object* feedback = vector->get(slot->value());
218 }
else if (feedback->IsAllocationSite() || feedback->IsJSFunction()) {
static Address target_address_at(Address pc, ConstantPoolArray *constant_pool)
static void set_target_address_at(Address pc, ConstantPoolArray *constant_pool, Address target, ICacheFlushMode icache_flush_mode=FLUSH_ICACHE_IF_NEEDED)
static Address target_address_from_return_address(Address pc)
IC::State FeedbackToState(Handle< TypeFeedbackVector > vector, Handle< Smi > slot) const
ConstantPoolArray * constant_pool()
static Code * GetCodeFromTargetAddress(Address address)
ExtraICState extra_ic_state()
bool is_inline_cache_stub()
byte * instruction_start()
bool has_break_points() const
static bool IsDebugBreak(Address addr)
IncrementalMarking * incremental_marking()
MarkCompactCollector * mark_compact_collector()
static void PostPatching(Address address, Code *target, Code *old_target)
Code * GetOriginalCode() const
static void SetTargetAtAddress(Address address, Code *target, ConstantPoolArray *constant_pool)
static Handle< Map > TypeToMap(HeapType *type, Isolate *isolate)
static Code * GetTargetAtAddress(Address address, ConstantPoolArray *constant_pool)
ConstantPoolArray * constant_pool() const
Handle< ConstantPoolArray > raw_constant_pool_
Isolate * isolate() const
Code * raw_target() const
static JSFunction * GetRootConstructor(TypeClass *type, Context *native_context)
ExtraICState extra_ic_state() const
Handle< Code > target() const
void set_target(Code *code)
ConstantPoolArray * raw_constant_pool() const
static Handle< Map > GetHandlerCacheHolder(HeapType *type, bool receiver_is_holder, Isolate *isolate, CacheHolderFlag *flag)
static Handle< Map > GetICCacheHolder(HeapType *type, Isolate *isolate, CacheHolderFlag *flag)
void RecordCodeTargetPatch(Code *host, Address pc, HeapObject *value)
Handle< Context > native_context()
Object * instance_prototype()
void set_target(Code *code)
void set_target(Code *code)
void RecordCodeTargetPatch(Address pc, Code *target)
void set_target(Code *code)
static StrictMode GetStrictMode(ExtraICState state)
StrictMode strict_mode() const
static Handle< Object > UninitializedSentinel(Isolate *isolate)
static Handle< Object > MegamorphicSentinel(Isolate *isolate)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
IN DWORD64 OUT PDWORD64 OUT PIMAGEHLP_SYMBOL64 Symbol
@ kCacheOnPrototypeReceiverIsPrimitive
@ kCacheOnPrototypeReceiverIsDictionary
Handle< T > handle(T *t, Isolate *isolate)
kFeedbackVectorOffset flag
Debugger support for the V8 JavaScript engine.