15 TEST_F(InstructionSelectorTest, ChangeFloat32ToFloat64WithParameter) {
17 m.Return(m.ChangeFloat32ToFloat64(m.Parameter(0)));
19 ASSERT_EQ(1U, s.size());
20 EXPECT_EQ(kSSECvtss2sd, s[0]->arch_opcode());
21 EXPECT_EQ(1U, s[0]->InputCount());
22 EXPECT_EQ(1U, s[0]->OutputCount());
28 m.Return(m.ChangeInt32ToInt64(m.Parameter(0)));
30 ASSERT_EQ(1U, s.size());
31 EXPECT_EQ(kX64Movsxlq, s[0]->arch_opcode());
37 m.Return(m.ChangeUint32ToUint64(m.Parameter(0)));
39 ASSERT_EQ(1U, s.size());
40 EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
44 TEST_F(InstructionSelectorTest, TruncateFloat64ToFloat32WithParameter) {
46 m.Return(m.TruncateFloat64ToFloat32(m.Parameter(0)));
48 ASSERT_EQ(1U, s.size());
49 EXPECT_EQ(kSSECvtsd2ss, s[0]->arch_opcode());
50 EXPECT_EQ(1U, s[0]->InputCount());
51 EXPECT_EQ(1U, s[0]->OutputCount());
57 m.Return(m.TruncateInt64ToInt32(m.Parameter(0)));
59 ASSERT_EQ(1U, s.size());
60 EXPECT_EQ(kX64Movl, s[0]->arch_opcode());
67 TEST_F(InstructionSelectorTest, BetterLeftOperandTestAddBinop) {
69 Node* param1 = m.Parameter(0);
70 Node* param2 = m.Parameter(1);
71 Node* add = m.Int32Add(param1, param2);
72 m.Return(m.Int32Add(add, param1));
74 ASSERT_EQ(2U, s.size());
75 EXPECT_EQ(kX64Add32, s[0]->arch_opcode());
76 ASSERT_EQ(2U, s[0]->InputCount());
77 ASSERT_TRUE(s[0]->InputAt(0)->IsUnallocated());
78 EXPECT_EQ(param2->id(), s.ToVreg(s[0]->InputAt(0)));
82 TEST_F(InstructionSelectorTest, BetterLeftOperandTestMulBinop) {
84 Node* param1 = m.Parameter(0);
85 Node* param2 = m.Parameter(1);
86 Node* mul = m.Int32Mul(param1, param2);
87 m.Return(m.Int32Mul(mul, param1));
89 ASSERT_EQ(2U, s.size());
90 EXPECT_EQ(kX64Imul32, s[0]->arch_opcode());
91 ASSERT_EQ(2U, s[0]->InputCount());
92 ASSERT_TRUE(s[0]->InputAt(0)->IsUnallocated());
93 EXPECT_EQ(param2->id(), s.ToVreg(s[0]->InputAt(0)));
112 return os << ost.
c_str();
131 typedef InstructionSelectorTestWithParam<MemoryAccess>
136 const MemoryAccess memacc = GetParam();
138 m.Return(m.Load(memacc.type, m.Parameter(0), m.Parameter(1)));
139 Stream s = m.Build();
140 ASSERT_EQ(1U, s.size());
141 EXPECT_EQ(memacc.load_opcode, s[0]->arch_opcode());
142 EXPECT_EQ(2U, s[0]->InputCount());
143 EXPECT_EQ(1U, s[0]->OutputCount());
148 const MemoryAccess memacc = GetParam();
150 m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2));
151 m.Return(m.Int32Constant(0));
152 Stream s = m.Build();
153 ASSERT_EQ(1U, s.size());
154 EXPECT_EQ(memacc.store_opcode, s[0]->arch_opcode());
155 EXPECT_EQ(3U, s[0]->InputCount());
156 EXPECT_EQ(0
U, s[0]->OutputCount());
167 class AddressingModeUnitTest :
public InstructionSelectorTest {
175 m->Return(
m->Int32Constant(0));
176 Stream s =
m->Build();
177 ASSERT_EQ(2U, s.size());
178 EXPECT_EQ(
mode, s[0]->addressing_mode());
179 EXPECT_EQ(
mode, s[1]->addressing_mode());
193 zero =
m->Int32Constant(0);
199 scales[0] =
m->Int32Constant(1);
200 scales[1] =
m->Int32Constant(2);
201 scales[2] =
m->Int32Constant(4);
202 scales[3] =
m->Int32Constant(8);
207 TEST_F(AddressingModeUnitTest, AddressingMode_MR) {
208 Node* base = base_reg;
210 Run(base, index, kMode_MR);
214 TEST_F(AddressingModeUnitTest, AddressingMode_MRI) {
215 Node* base = base_reg;
216 Node* index = non_zero;
217 Run(base, index, kMode_MRI);
221 TEST_F(AddressingModeUnitTest, AddressingMode_MR1) {
222 Node* base = base_reg;
223 Node* index = index_reg;
224 Run(base, index, kMode_MR1);
228 TEST_F(AddressingModeUnitTest, AddressingMode_MRN) {
229 AddressingMode expected[] = {kMode_MR1, kMode_MR2, kMode_MR4, kMode_MR8};
232 Node* base = base_reg;
233 Node* index = m->Int32Mul(index_reg, scales[
i]);
234 Run(base, index, expected[
i]);
239 TEST_F(AddressingModeUnitTest, AddressingMode_MR1I) {
240 Node* base = base_reg;
241 Node* index = m->Int32Add(index_reg, non_zero);
242 Run(base, index, kMode_MR1I);
246 TEST_F(AddressingModeUnitTest, AddressingMode_MRNI) {
247 AddressingMode expected[] = {kMode_MR1I, kMode_MR2I, kMode_MR4I, kMode_MR8I};
250 Node* base = base_reg;
251 Node* index = m->Int32Add(m->Int32Mul(index_reg, scales[
i]), non_zero);
252 Run(base, index, expected[
i]);
257 TEST_F(AddressingModeUnitTest, AddressingMode_M1) {
258 Node* base = null_ptr;
259 Node* index = index_reg;
260 Run(base, index, kMode_M1);
264 TEST_F(AddressingModeUnitTest, AddressingMode_MN) {
265 AddressingMode expected[] = {kMode_M1, kMode_M2, kMode_M4, kMode_M8};
268 Node* base = null_ptr;
269 Node* index = m->Int32Mul(index_reg, scales[
i]);
270 Run(base, index, expected[
i]);
275 TEST_F(AddressingModeUnitTest, AddressingMode_M1I) {
276 Node* base = null_ptr;
277 Node* index = m->Int32Add(index_reg, non_zero);
278 Run(base, index, kMode_M1I);
282 TEST_F(AddressingModeUnitTest, AddressingMode_MNI) {
283 AddressingMode expected[] = {kMode_M1I, kMode_M2I, kMode_M4I, kMode_M8I};
286 Node* base = null_ptr;
287 Node* index = m->Int32Add(m->Int32Mul(index_reg, scales[
i]), non_zero);
288 Run(base, index, expected[
i]);
const char * c_str() const
~AddressingModeUnitTest()
void Run(Node *base, Node *index, AddressingMode mode)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
std::ostream & operator<<(std::ostream &os, const MachineType &type)
static const MemoryAccess kMemoryAccesses[]
TEST_P(InstructionSelectorDPITest, Parameters)
InstructionSelectorTestWithParam< MemoryAccess > InstructionSelectorMemoryAccessTest
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorDPITest, ::testing::ValuesIn(kDPIs))
TEST_F(InstructionSelectorTest, ChangeFloat32ToFloat64WithParameter)
Debugger support for the V8 JavaScript engine.