5 #ifndef V8_LOG_UTILS_H_
6 #define V8_LOG_UTILS_H_
25 return FLAG_log || FLAG_log_api || FLAG_log_code || FLAG_log_gc
26 || FLAG_log_handles || FLAG_log_suspect || FLAG_log_regexp
27 || FLAG_ll_prof || FLAG_perf_basic_prof || FLAG_perf_jit_prof
28 || FLAG_log_internal_timer_events;
59 void Append(
const char* format, ...);
62 void AppendVA(
const char* format, va_list args);
108 DCHECK(
static_cast<size_t>(length) == rv);
void AppendAddress(Address addr)
void AppendDoubleQuotedString(const char *string)
void AppendVA(const char *format, va_list args)
void AppendDetailed(String *str, bool show_impl_info)
void Append(const char c)
void Append(const char *format,...)
void AppendStringPart(const char *str, int len)
base::LockGuard< base::Mutex > lock_guard_
void AppendSymbolName(Symbol *symbol)
void Initialize(const char *log_file_name)
static const int kMessageBufferSize
void OpenFile(const char *name)
int WriteToFile(const char *msg, int length)
static bool InitLogAtStart()
static const char *const kLogToTemporaryFile
static const char *const kLogToConsole
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
Debugger support for the V8 JavaScript engine.