5 #ifndef V8_SAFEPOINT_TABLE_H_
6 #define V8_SAFEPOINT_TABLE_H_
28 bool Equals(
const SafepointEntry& other)
const {
29 return info_ == other.info_ && bits_ == other.bits_;
39 return DeoptimizationIndexField::decode(info_);
42 static const int kArgumentsFieldBits = 3;
43 static const int kSaveDoublesFieldBits = 1;
44 static const int kDeoptIndexBits =
45 32 - kArgumentsFieldBits - kSaveDoublesFieldBits;
47 public BitField<int, 0, kDeoptIndexBits> {};
51 kArgumentsFieldBits> {};
54 kDeoptIndexBits + kArgumentsFieldBits,
55 kSaveDoublesFieldBits> { };
59 return ArgumentsField::decode(info_);
64 return SaveDoublesField::decode(info_);
87 (length_ * (kPcAndDeoptimizationIndexSize + entry_size_));
89 unsigned length()
const {
return length_; }
97 SafepointEntry
GetEntry(
unsigned index)
const {
101 return SafepointEntry(info, bits);
110 static const uint8_t kNoRegisters = 0xFF;
112 static const int kLengthOffset = 0;
113 static const int kEntrySizeOffset = kLengthOffset +
kIntSize;
114 static const int kHeaderSize = kEntrySizeOffset +
kIntSize;
117 static const int kDeoptimizationIndexSize =
kIntSize;
118 static const int kPcAndDeoptimizationIndexSize =
119 kPcSize + kDeoptimizationIndexSize;
122 return pc_and_deoptimization_indexes_ +
123 (index * kPcAndDeoptimizationIndexSize);
127 return GetPcOffsetLocation(index) + kPcSize;
131 uint8_t
byte,
int digits);
141 friend class SafepointTableBuilder;
142 friend class SafepointEntry;
152 kWithRegisters = 1 << 0,
153 kWithDoubles = 1 << 1,
154 kWithRegistersAndDoubles = kWithRegisters | kWithDoubles
162 static const int kNoDeoptimizationIndex =
163 (1 << (SafepointEntry::kDeoptIndexBits)) - 1;
170 : indexes_(indexes), registers_(registers) {}
174 friend class SafepointTableBuilder;
181 : deoptimization_info_(32, zone),
182 deopt_index_list_(32, zone),
184 registers_(32, zone),
186 last_lazy_safepoint_(0),
194 Safepoint::Kind kind,
196 Safepoint::DeoptMode
mode);
202 last_lazy_safepoint_ = deopt_index_list_.length();
Safepoint(ZoneList< int > *indexes, ZoneList< int > *registers)
Safepoint DefineSafepoint(Assembler *assembler, Safepoint::Kind kind, int arguments, Safepoint::DeoptMode mode)
DISALLOW_COPY_AND_ASSIGN(SafepointTable)
SafepointEntry GetEntry(unsigned index) const
SafepointTableBuilder(Zone *zone)
ZoneList< DeoptimizationInfo > deoptimization_info_
unsigned entry_size() const
Address GetInfoLocation(unsigned index) const
unsigned GetPcOffset(unsigned index) const
ZoneList< ZoneList< int > * > indexes_
uint32_t EncodeExceptPC(const DeoptimizationInfo &info, unsigned index)
DISALLOW_COPY_AND_ASSIGN(SafepointTableBuilder)
unsigned GetCodeOffset() const
Address pc_and_deoptimization_indexes_
ZoneList< unsigned > deopt_index_list_
int argument_count() const
void BumpLastLazySafepointIndex()
ZoneList< int > * indexes_
SafepointEntry(unsigned info, uint8_t *bits)
bool HasRegisters() const
SafepointTable(Code *code)
bool Equals(const SafepointEntry &other) const
ZoneList< ZoneList< int > * > registers_
void PrintEntry(unsigned index, OStream &os) const
ZoneList< int > * registers_
Address GetPcOffsetLocation(unsigned index) const
bool HasRegisterAt(int reg_index) const
DisallowHeapAllocation no_allocation_
int deoptimization_index() const
SafepointEntry FindEntry(Address pc) const
void DefinePointerSlot(int index, Zone *zone)
static void PrintBits(OStream &os, uint8_t byte, int digits)
void RecordLazyDeoptimizationIndex(int index)
void DefinePointerRegister(Register reg, Zone *zone)
void Emit(Assembler *assembler, int bits_per_entry)
static uint8_t & uint8_at(Address addr)
static uint32_t & uint32_at(Address addr)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
Debugger support for the V8 JavaScript engine.