#include <hydrogen-instructions.h>

Collaboration diagram for v8::internal::FINAL< kOperandKind, kNumCachedOperands >::BitwiseDecompositionResult:

Public Member Functions
	BitwiseDecompositionResult ()

Public Attributes
HValue *	base

int32_t	and_mask

int32_t	or_mask

HValue *	context

Detailed Description

template<LOperand::Kind kOperandKind, int kNumCachedOperands>
struct v8::internal::FINAL< kOperandKind, kNumCachedOperands >::BitwiseDecompositionResult

Definition at line 3161 of file hydrogen-instructions.h.

Constructor & Destructor Documentation

◆ BitwiseDecompositionResult()

template<LOperand::Kind kOperandKind, int kNumCachedOperands>

v8::internal::FINAL< kOperandKind, kNumCachedOperands >::BitwiseDecompositionResult::BitwiseDecompositionResult ( )

inline

Definition at line 3167 of file hydrogen-instructions.h.

3168 : base(NULL), and_mask(0), or_mask(0), context(NULL) {}

NULL

enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL

Definition: flag-definitions.h:407

v8::internal::FINAL::BitwiseDecompositionResult::base

HValue * base

Definition: hydrogen-instructions.h:3162

v8::internal::FINAL::BitwiseDecompositionResult::or_mask

int32_t or_mask

Definition: hydrogen-instructions.h:3164

v8::internal::FINAL::BitwiseDecompositionResult::context

HValue * context

Definition: hydrogen-instructions.h:3165

v8::internal::FINAL::BitwiseDecompositionResult::and_mask

int32_t and_mask