35 #define MAJOR_VERSION 3
36 #define MINOR_VERSION 29
37 #define BUILD_NUMBER 93
41 #define IS_CANDIDATE_VERSION 0
48 #if IS_CANDIDATE_VERSION
49 #define CANDIDATE_STRING " (candidate)"
51 #define CANDIDATE_STRING ""
58 #define VERSION_STRING \
59 S(MAJOR_VERSION) "." S(MINOR_VERSION) "." S(BUILD_NUMBER) "." \
60 S(PATCH_LEVEL) CANDIDATE_STRING
62 #define VERSION_STRING \
63 S(MAJOR_VERSION) "." S(MINOR_VERSION) "." S(BUILD_NUMBER) \
80 const char* candidate =
IsCandidate() ?
" (candidate)" :
"";
82 const char* is_simulator =
" SIMULATOR";
84 const char* is_simulator =
"";
102 const char* candidate =
IsCandidate() ?
"-candidate" :
"";
104 SNPrintF(str,
"libv8-%d.%d.%d.%d%s.so",
107 SNPrintF(str,
"libv8-%d.%d.%d%s.so",
static const char * version_string_
static const char * soname_
static void GetSONAME(Vector< char > str)
static bool IsCandidate()
static void GetString(Vector< char > str)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
int SNPrintF(Vector< char > str, const char *format,...)
Debugger support for the V8 JavaScript engine.
#define IS_CANDIDATE_VERSION