6041 RegExpCompiler compiler(data->capture_count, ignore_case, is_one_byte, zone);
6044 static const int kSampleSize = 128;
6047 int chars_sampled = 0;
6048 int half_way = (sample_subject->length() - kSampleSize) / 2;
6049 for (
int i =
Max(0, half_way);
6050 i < sample_subject->length() && chars_sampled < kSampleSize;
6051 i++, chars_sampled++) {
6052 compiler.frequency_collator()->CountCharacter(sample_subject->Get(
i));
6056 RegExpNode* captured_body = RegExpCapture::ToNode(data->tree,
6060 RegExpNode* node = captured_body;
6061 bool is_end_anchored = data->tree->IsAnchoredAtEnd();
6062 bool is_start_anchored = data->tree->IsAnchoredAtStart();
6063 int max_length = data->tree->max_match();
6064 if (!is_start_anchored && !is_sticky) {
6067 RegExpNode* loop_node =
6068 RegExpQuantifier::ToNode(0,
6071 new(zone) RegExpCharacterClass(
'*'),
6074 data->contains_anchor);
6076 if (data->contains_anchor) {
6079 ChoiceNode* first_step_node =
new(zone) ChoiceNode(2, zone);
6080 first_step_node->AddAlternative(GuardedAlternative(captured_body));
6081 first_step_node->AddAlternative(GuardedAlternative(
6082 new(zone) TextNode(
new(zone) RegExpCharacterClass(
'*'), loop_node)));
6083 node = first_step_node;
6099 Analysis analysis(ignore_case, is_one_byte);
6100 analysis.EnsureAnalyzed(node);
6101 if (analysis.has_failed()) {
6102 const char* error_message = analysis.error_message();
6103 return CompilationResult(zone->isolate(), error_message);
6107 #ifndef V8_INTERPRETED_REGEXP
6114 #if V8_TARGET_ARCH_IA32
6115 RegExpMacroAssemblerIA32 macro_assembler(
mode, (data->capture_count + 1) * 2,
6117 #elif V8_TARGET_ARCH_X64
6118 RegExpMacroAssemblerX64 macro_assembler(
mode, (data->capture_count + 1) * 2,
6120 #elif V8_TARGET_ARCH_ARM
6121 RegExpMacroAssemblerARM macro_assembler(
mode, (data->capture_count + 1) * 2,
6123 #elif V8_TARGET_ARCH_ARM64
6124 RegExpMacroAssemblerARM64 macro_assembler(
mode, (data->capture_count + 1) * 2,
6126 #elif V8_TARGET_ARCH_MIPS
6127 RegExpMacroAssemblerMIPS macro_assembler(
mode, (data->capture_count + 1) * 2,
6129 #elif V8_TARGET_ARCH_MIPS64
6130 RegExpMacroAssemblerMIPS macro_assembler(
mode, (data->capture_count + 1) * 2,
6132 #elif V8_TARGET_ARCH_X87
6133 RegExpMacroAssemblerX87 macro_assembler(
mode, (data->capture_count + 1) * 2,
6136 #error "Unsupported architecture"
6141 EmbeddedVector<byte, 1024> codes;
6142 RegExpMacroAssemblerIrregexp macro_assembler(codes, zone);
6147 static const int kMaxBacksearchLimit = 1024;
6148 if (is_end_anchored &&
6149 !is_start_anchored &&
6150 max_length < kMaxBacksearchLimit) {
6151 macro_assembler.SetCurrentPositionFromEnd(max_length);
6155 macro_assembler.set_global_mode(
6156 (data->tree->min_match() > 0)
6161 return compiler.Assemble(¯o_assembler,
6163 data->capture_count,
static const int kMaxRecursion
@ GLOBAL_NO_ZERO_LENGTH_CHECK
static const int kMaxRegister
static const int kInfinity
static Handle< String > Flatten(Handle< String > string, PretenureFlag pretenure=NOT_TENURED)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
static LifetimePosition Max(LifetimePosition a, LifetimePosition b)
static RegExpEngine::CompilationResult IrregexpRegExpTooBig(Isolate *isolate)