V8 Project
code-stubs-mips.h
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1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4 
5 #ifndef V8_MIPS_CODE_STUBS_ARM_H_
6 #define V8_MIPS_CODE_STUBS_ARM_H_
7 
8 namespace v8 {
9 namespace internal {
10 
11 
12 void ArrayNativeCode(MacroAssembler* masm, Label* call_generic_code);
13 
14 
15 class StringHelper : public AllStatic {
16  public:
17  // Generate code for copying a large number of characters. This function
18  // is allowed to spend extra time setting up conditions to make copying
19  // faster. Copying of overlapping regions is not supported.
20  // Dest register ends at the position after the last character written.
22  Register dest,
23  Register src,
24  Register count,
25  Register scratch,
26  String::Encoding encoding);
27 
28  // Compares two flat one-byte strings and returns result in v0.
30  MacroAssembler* masm, Register left, Register right, Register scratch1,
31  Register scratch2, Register scratch3, Register scratch4);
32 
33  // Compares two flat one-byte strings for equality and returns result in v0.
35  Register left, Register right,
36  Register scratch1,
37  Register scratch2,
38  Register scratch3);
39 
40  private:
42  MacroAssembler* masm, Register left, Register right, Register length,
43  Register scratch1, Register scratch2, Register scratch3,
44  Label* chars_not_equal);
45 
47 };
48 
49 
51  public:
52  explicit StoreRegistersStateStub(Isolate* isolate)
53  : PlatformCodeStub(isolate) {}
54 
55  static void GenerateAheadOfTime(Isolate* isolate);
56 
57  private:
60 };
61 
62 
64  public:
66  : PlatformCodeStub(isolate) {}
67 
68  static void GenerateAheadOfTime(Isolate* isolate);
69 
70  private:
73 };
74 
75 
76 // This stub can convert a signed int32 to a heap number (double). It does
77 // not work for int32s that are in Smi range! No GC occurs during this stub
78 // so you don't have to set up the frame.
80  public:
83  Register scratch2)
84  : PlatformCodeStub(isolate) {
85  minor_key_ = IntRegisterBits::encode(the_int.code()) |
88  SignRegisterBits::encode(scratch2.code());
93  }
94 
96 
97  private:
98  Register the_int() const {
99  return Register::from_code(IntRegisterBits::decode(minor_key_));
100  }
101 
104  }
105 
106  Register scratch() const {
108  }
109 
110  Register sign() const {
111  return Register::from_code(SignRegisterBits::decode(minor_key_));
112  }
113 
114  // Minor key encoding in 16 bits.
115  class IntRegisterBits: public BitField<int, 0, 4> {};
116  class HeapNumberRegisterBits: public BitField<int, 4, 4> {};
117  class ScratchRegisterBits: public BitField<int, 8, 4> {};
118  class SignRegisterBits: public BitField<int, 12, 4> {};
119 
121  DEFINE_PLATFORM_CODE_STUB(WriteInt32ToHeapNumber, PlatformCodeStub);
122 };
123 
124 
125 class RecordWriteStub: public PlatformCodeStub {
126  public:
128  Register object,
129  Register value,
132  SaveFPRegsMode fp_mode)
133  : PlatformCodeStub(isolate),
134  regs_(object, // An input reg.
135  address, // An input reg.
136  value) { // One scratch reg.
137  minor_key_ = ObjectBits::encode(object.code()) |
142  }
143 
145  : PlatformCodeStub(key, isolate), regs_(object(), address(), value()) {}
146 
147  enum Mode {
149  INCREMENTAL,
151  };
152 
153  virtual bool SometimesSetsUpAFrame() { return false; }
154 
155  static void PatchBranchIntoNop(MacroAssembler* masm, int pos) {
156  const unsigned offset = masm->instr_at(pos) & kImm16Mask;
157  masm->instr_at_put(pos, BNE | (zero_reg.code() << kRsShift) |
158  (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
159  DCHECK(Assembler::IsBne(masm->instr_at(pos)));
160  }
161 
162  static void PatchNopIntoBranch(MacroAssembler* masm, int pos) {
163  const unsigned offset = masm->instr_at(pos) & kImm16Mask;
164  masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) |
165  (zero_reg.code() << kRtShift) | (offset & kImm16Mask));
166  DCHECK(Assembler::IsBeq(masm->instr_at(pos)));
167  }
168 
169  static Mode GetMode(Code* stub) {
170  Instr first_instruction = Assembler::instr_at(stub->instruction_start());
171  Instr second_instruction = Assembler::instr_at(stub->instruction_start() +
173 
174  if (Assembler::IsBeq(first_instruction)) {
175  return INCREMENTAL;
176  }
177 
178  DCHECK(Assembler::IsBne(first_instruction));
179 
180  if (Assembler::IsBeq(second_instruction)) {
181  return INCREMENTAL_COMPACTION;
182  }
183 
184  DCHECK(Assembler::IsBne(second_instruction));
185 
186  return STORE_BUFFER_ONLY;
187  }
188 
189  static void Patch(Code* stub, Mode mode) {
190  MacroAssembler masm(NULL,
191  stub->instruction_start(),
192  stub->instruction_size());
193  switch (mode) {
194  case STORE_BUFFER_ONLY:
195  DCHECK(GetMode(stub) == INCREMENTAL ||
197  PatchBranchIntoNop(&masm, 0);
199  break;
200  case INCREMENTAL:
201  DCHECK(GetMode(stub) == STORE_BUFFER_ONLY);
202  PatchNopIntoBranch(&masm, 0);
203  break;
205  DCHECK(GetMode(stub) == STORE_BUFFER_ONLY);
207  break;
208  }
209  DCHECK(GetMode(stub) == mode);
212  }
213 
215 
216  private:
217  // This is a helper class for freeing up 3 scratch registers. The input is
218  // two registers that must be preserved and one scratch register provided by
219  // the caller.
220  class RegisterAllocation {
221  public:
225  : object_(object),
226  address_(address),
228  DCHECK(!AreAliased(scratch0, object, address, no_reg));
230  }
231 
232  void Save(MacroAssembler* masm) {
234  // We don't have to save scratch0_ because it was given to us as
235  // a scratch register.
236  masm->push(scratch1_);
237  }
238 
239  void Restore(MacroAssembler* masm) {
240  masm->pop(scratch1_);
241  }
242 
243  // If we have to call into C then we need to save and restore all caller-
244  // saved registers that were not already preserved. The scratch registers
245  // will be restored by other means so we don't bother pushing them here.
247  masm->MultiPush((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
248  if (mode == kSaveFPRegs) {
250  }
251  }
252 
255  if (mode == kSaveFPRegs) {
257  }
258  masm->MultiPop((kJSCallerSaved | ra.bit()) & ~scratch1_.bit());
259  }
260 
261  inline Register object() { return object_; }
262  inline Register address() { return address_; }
263  inline Register scratch0() { return scratch0_; }
264  inline Register scratch1() { return scratch1_; }
265 
266  private:
271 
272  friend class RecordWriteStub;
273  };
274 
278  };
279 
280  virtual inline Major MajorKey() const FINAL OVERRIDE { return RecordWrite; }
281 
282  virtual void Generate(MacroAssembler* masm) OVERRIDE;
285  MacroAssembler* masm,
287  Mode mode);
289 
290  void Activate(Code* code) {
292  }
293 
294  Register object() const {
295  return Register::from_code(ObjectBits::decode(minor_key_));
296  }
297 
298  Register value() const {
299  return Register::from_code(ValueBits::decode(minor_key_));
300  }
301 
302  Register address() const {
303  return Register::from_code(AddressBits::decode(minor_key_));
304  }
305 
307  return RememberedSetActionBits::decode(minor_key_);
308  }
309 
311  return SaveFPRegsModeBits::decode(minor_key_);
312  }
313 
314  class ObjectBits: public BitField<int, 0, 5> {};
315  class ValueBits: public BitField<int, 5, 5> {};
316  class AddressBits: public BitField<int, 10, 5> {};
317  class RememberedSetActionBits: public BitField<RememberedSetAction, 15, 1> {};
318  class SaveFPRegsModeBits: public BitField<SaveFPRegsMode, 16, 1> {};
319 
320  Label slow_;
321  RegisterAllocation regs_;
322 
324 };
325 
326 
327 // Trampoline stub to call into native code. To call safely into native code
328 // in the presence of compacting GC (which can move code objects) we need to
329 // keep the code which called into native pinned in the memory. Currently the
330 // simplest approach is to generate such stub early enough so it can never be
331 // moved by GC
332 class DirectCEntryStub: public PlatformCodeStub {
333  public:
334  explicit DirectCEntryStub(Isolate* isolate) : PlatformCodeStub(isolate) {}
335  void GenerateCall(MacroAssembler* masm, Register target);
336 
337  private:
338  bool NeedsImmovableCode() { return true; }
339 
342 };
343 
344 
346  public:
348 
350  : PlatformCodeStub(isolate) {
351  minor_key_ = LookupModeBits::encode(mode);
352  }
353 
355  Label* miss,
356  Label* done,
357  Register receiver,
358  Register properties,
360  Register scratch0);
361 
363  Label* miss,
364  Label* done,
365  Register elements,
366  Register name,
367  Register r0,
368  Register r1);
369 
370  virtual bool SometimesSetsUpAFrame() { return false; }
371 
372  private:
373  static const int kInlinedProbes = 4;
374  static const int kTotalProbes = 20;
375 
376  static const int kCapacityOffset =
379 
380  static const int kElementsStartOffset =
383 
384  LookupMode mode() const { return LookupModeBits::decode(minor_key_); }
385 
386  class LookupModeBits: public BitField<LookupMode, 0, 1> {};
387 
390 };
391 
392 
393 } } // namespace v8::internal
394 
395 #endif // V8_MIPS_CODE_STUBS_ARM_H_
static const int kInstrSize
static bool IsBne(Instr instr)
void instr_at_put(int pos, Instr instr)
static bool IsBeq(Instr instr)
static bool is_valid(T value)
Definition: utils.h:212
static U encode(T value)
Definition: utils.h:217
static T decode(U value)
Definition: utils.h:228
int instruction_size() const
byte * instruction_start()
Definition: objects-inl.h:6176
static void FlushICache(void *start, size_t size)
DirectCEntryStub(Isolate *isolate)
void GenerateCall(MacroAssembler *masm, Register target)
DEFINE_PLATFORM_CODE_STUB(DirectCEntry, PlatformCodeStub)
Source to read snapshot and builtins files from.
Definition: lithium-arm.h:372
static const int kHeaderSize
Definition: objects.h:2393
static const int kElementsStartIndex
Definition: objects.h:3274
static const int kCapacityIndex
Definition: objects.h:3272
Heap * GetHeap() const
Definition: objects-inl.h:1379
IncrementalMarking * incremental_marking()
Definition: heap.h:1205
void MultiPushFPU(RegList regs)
void MultiPush(RegList regs)
void MultiPopFPU(RegList regs)
void MultiPop(RegList regs)
NameDictionaryLookupStub(Isolate *isolate, LookupMode mode)
static void GeneratePositiveLookup(MacroAssembler *masm, Label *miss, Label *done, Register elements, Register name, Register r0, Register r1)
DEFINE_PLATFORM_CODE_STUB(NameDictionaryLookup, PlatformCodeStub)
static void GenerateNegativeLookup(MacroAssembler *masm, Label *miss, Label *done, Register receiver, Register properties, Handle< Name > name, Register scratch0)
void SaveCallerSaveRegisters(MacroAssembler *masm, SaveFPRegsMode mode)
RegisterAllocation(Register object, Register address, Register scratch0)
void RestoreCallerSaveRegisters(MacroAssembler *masm, SaveFPRegsMode mode)
void GenerateIncremental(MacroAssembler *masm, Mode mode)
void InformIncrementalMarker(MacroAssembler *masm)
RememberedSetAction remembered_set_action() const
static void PatchBranchIntoNop(MacroAssembler *masm, int pos)
static void PatchNopIntoBranch(MacroAssembler *masm, int pos)
SaveFPRegsMode save_fp_regs_mode() const
RecordWriteStub(Isolate *isolate, Register object, Register value, Register address, RememberedSetAction remembered_set_action, SaveFPRegsMode fp_mode)
RecordWriteStub(uint32_t key, Isolate *isolate)
virtual Major MajorKey() const FINAL OVERRIDE
void CheckNeedsToInformIncrementalMarker(MacroAssembler *masm, OnNoNeedToInformIncrementalMarker on_no_need, Mode mode)
DISALLOW_COPY_AND_ASSIGN(RecordWriteStub)
static void Patch(Code *stub, Mode mode)
static Mode GetMode(Code *stub)
virtual void Generate(MacroAssembler *masm) OVERRIDE
DEFINE_PLATFORM_CODE_STUB(RestoreRegistersState, PlatformCodeStub)
static void GenerateAheadOfTime(Isolate *isolate)
static void GenerateAheadOfTime(Isolate *isolate)
DEFINE_PLATFORM_CODE_STUB(StoreRegistersState, PlatformCodeStub)
DISALLOW_IMPLICIT_CONSTRUCTORS(StringHelper)
static void GenerateCompareFlatOneByteStrings(MacroAssembler *masm, Register left, Register right, Register scratch1, Register scratch2, Register scratch3, Register scratch4)
static void GenerateCopyCharacters(MacroAssembler *masm, Register dest, Register src, Register count, Register scratch, String::Encoding encoding)
static void GenerateOneByteCharsCompareLoop(MacroAssembler *masm, Register left, Register right, Register length, Register scratch1, Register scratch2, Register scratch3, Label *chars_not_equal)
static void GenerateFlatOneByteStringEquals(MacroAssembler *masm, Register left, Register right, Register scratch1, Register scratch2, Register scratch3)
DEFINE_PLATFORM_CODE_STUB(WriteInt32ToHeapNumber, PlatformCodeStub)
static void GenerateFixedRegStubsAheadOfTime(Isolate *isolate)
WriteInt32ToHeapNumberStub(Isolate *isolate, Register the_int, Register the_heap_number, Register scratch, Register scratch2)
#define OVERRIDE
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
Definition: logging.h:205
const int kPointerSize
Definition: globals.h:129
const int kRtShift
const RegList kJSCallerSaved
Definition: frames-arm.h:24
bool AreAliased(const CPURegister &reg1, const CPURegister &reg2, const CPURegister &reg3=NoReg, const CPURegister &reg4=NoReg, const CPURegister &reg5=NoReg, const CPURegister &reg6=NoReg, const CPURegister &reg7=NoReg, const CPURegister &reg8=NoReg)
const Register r0
void ArrayNativeCode(MacroAssembler *masm, Label *call_generic_code)
const int kRsShift
const Register r1
const Register no_reg
Register GetRegisterThatIsNotOneOf(Register reg1, Register reg2=no_reg, Register reg3=no_reg, Register reg4=no_reg, Register reg5=no_reg, Register reg6=no_reg)
const RegList kCallerSavedFPU
Definition: frames-mips.h:66
Debugger support for the V8 JavaScript engine.
Definition: accessors.cc:20
static Register from_code(int code)