17 const int kCallInstructionSizeInWords = 6;
23 Address code_start_address = code->instruction_start();
26 code->InvalidateRelocation();
28 if (FLAG_zap_code_space) {
30 byte* pointer = code->FindCodeAgeSequence();
31 if (pointer !=
NULL) {
34 pointer = code->instruction_start();
36 CodePatcher patcher(pointer, 1);
37 patcher.masm()->break_(0xCC);
39 DeoptimizationInputData* data =
40 DeoptimizationInputData::cast(code->deoptimization_data());
41 int osr_offset = data->OsrPcOffset()->value();
43 CodePatcher osr_patcher(code->instruction_start() + osr_offset, 1);
44 osr_patcher.masm()->break_(0xCC);
48 DeoptimizationInputData* deopt_data =
49 DeoptimizationInputData::cast(code->deoptimization_data());
55 for (
int i = 0;
i < deopt_data->DeoptCount();
i++) {
56 if (deopt_data->Pc(
i)->value() == -1)
continue;
57 Address call_address = code_start_address + deopt_data->Pc(
i)->value();
64 CodePatcher patcher(call_address, call_size_in_words);
67 call_address >= prev_call_address +
patch_size());
71 prev_call_address = call_address;
99 FrameDescription* output_frame, CodeStubDescriptor* descriptor) {
100 ApiFunction
function(descriptor->deoptimization_handler());
101 ExternalReference xref(&
function, ExternalReference::BUILTIN_CALL,
isolate_);
102 intptr_t handler =
reinterpret_cast<intptr_t
>(xref.address());
103 int params = descriptor->GetHandlerParameterCount();
104 output_frame->SetRegister(
s0.
code(), params);
106 output_frame->SetRegister(
s2.
code(), handler);
113 output_frame->SetDoubleRegister(
i, double_value);
129 void Deoptimizer::EntryGenerator::Generate() {
137 RegList saved_regs = restored_regs |
sp.
bit() | ra.bit();
139 const int kDoubleRegsSize =
143 __ Dsubu(
sp,
sp, Operand(kDoubleRegsSize));
154 if ((saved_regs & (1 <<
i)) != 0) {
159 const int kSavedRegistersAreaSize =
172 __ Dsubu(a4,
fp, a4);
175 __ PrepareCallCFunction(6, a5);
177 __ li(a1, Operand(type()));
183 __ li(a5, Operand(ExternalReference::isolate_address(isolate())));
187 __ li(a5, Operand(ExternalReference::isolate_address(isolate())));
192 AllowExternalCallThatCantCauseGC scope(masm());
193 __ CallCFunction(ExternalReference::new_deoptimizer_function(isolate()), 6);
206 if ((saved_regs & (1 <<
i)) != 0) {
209 }
else if (FLAG_debug_code) {
231 __ Daddu(a2, a2,
sp);
238 Label pop_loop_header;
239 __ BranchShort(&pop_loop_header);
243 __ daddiu(a3, a3,
sizeof(uint64_t));
244 __ bind(&pop_loop_header);
245 __ BranchShort(&pop_loop,
ne, a2, Operand(
sp));
249 __ PrepareCallCFunction(1, a1);
252 AllowExternalCallThatCantCauseGC scope(masm());
254 ExternalReference::compute_output_frames_function(isolate()), 1);
259 Label outer_push_loop, inner_push_loop,
260 outer_loop_header, inner_loop_header;
266 __ daddu(a1, a4, a1);
267 __ jmp(&outer_loop_header);
268 __ bind(&outer_push_loop);
272 __ jmp(&inner_loop_header);
273 __ bind(&inner_push_loop);
274 __ Dsubu(a3, a3, Operand(
sizeof(uint64_t)));
275 __ Daddu(a6, a2, Operand(a3));
278 __ bind(&inner_loop_header);
279 __ BranchShort(&inner_push_loop,
ne, a3, Operand(zero_reg));
282 __ bind(&outer_loop_header);
283 __ BranchShort(&outer_push_loop,
lt, a4, Operand(a1));
304 DCHECK(!(at.bit() & restored_regs));
309 if ((restored_regs & (1 <<
i)) != 0) {
314 __ InitializeRootRegister();
319 __ stop(
"Unreachable.");
332 __ bind(&table_start);
341 __ Daddu(t9, t9, remaining_entries);
355 DCHECK_EQ(masm()->SizeOfCodeGeneratedSince(&table_start),
361 SetFrameSlot(offset, value);
366 SetFrameSlot(offset, value);
static const int kInstrSize
friend class BlockTrampolinePoolScope
virtual void GeneratePrologue()
static int output_offset()
static const int table_entry_size_
void CopyDoubleRegisters(FrameDescription *output_frame)
static Address GetDeoptimizationEntry(Isolate *isolate, int id, BailoutType type, GetEntryMode mode=ENSURE_ENTRY_CODE)
static int input_offset()
static void PatchCodeForDeoptimization(Isolate *isolate, Code *code)
static int output_count_offset()
void SetPlatformCompiledStubRegisters(FrameDescription *output_frame, CodeStubDescriptor *desc)
bool HasAlignmentPadding(JSFunction *function)
FrameDescription * input_
Isolate * isolate() const
void FillInputFrame(Address tos, JavaScriptFrame *frame)
static int frame_size_offset()
void SetCallerFp(unsigned offset, intptr_t value)
uint32_t GetFrameSize() const
static int continuation_offset()
static int frame_content_offset()
void SetCallerConstantPool(unsigned offset, intptr_t value)
static int state_offset()
static int registers_offset()
double GetDoubleRegister(unsigned n) const
static int double_registers_offset()
void SetRegister(unsigned n, intptr_t value)
void SetCallerPc(unsigned offset, intptr_t value)
void SetFrameSlot(unsigned offset, intptr_t value)
void SetDoubleRegister(unsigned n, double value)
static const int kFunctionOffset
static int CallSize(Register target, Condition cond=al)
static uint64_t & uint64_at(Address addr)
static const AbiVariants kMipsAbi
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
#define DCHECK_EQ(v1, v2)
const uint32_t kDebugZapValue
const RegList kJSCallerSaved
const RegList kCalleeSaved
const int kPointerSizeLog2
MemOperand CFunctionArgumentOperand(int index)
Register ToRegister(int num)
const unsigned kNumberOfRegisters
static const int kNoCodeAgeSequenceLength
Debugger support for the V8 JavaScript engine.
static int NumAllocatableRegisters()
static const int kMaxNumRegisters
static FPURegister FromAllocationIndex(int index)
static const int kMaxNumAllocatableRegisters
static int NumAllocatableRegisters()
static const int kNumRegisters