11 : count_(0), enabled_(
false), type_(type) {
68 {
"Move Immediate",
Gauge},
69 {
"Add/Sub DP",
Gauge},
70 {
"Logical DP",
Gauge},
71 {
"Other Int DP",
Gauge},
74 {
"Conditional Select",
Gauge},
75 {
"Conditional Compare",
Gauge},
77 {
"Unconditional Branch",
Gauge},
78 {
"Compare and Branch",
Gauge},
79 {
"Test and Branch",
Gauge},
80 {
"Conditional Branch",
Gauge},
82 {
"Load Integer",
Gauge},
85 {
"Load Literal",
Gauge},
87 {
"Store Integer",
Gauge},
89 {
"Store Pair",
Gauge},
91 {
"PC Addressing",
Gauge},
98 : output_stream_(stderr), sample_period_(sample_period) {
102 if (datafile !=
NULL) {
105 fprintf(stderr,
"Can't open output file %s. Using stderr.\n", datafile);
117 for (
int i = 0;
i < num_counters;
i++) {
131 std::list<Counter*>::iterator it;
158 std::list<Counter*>::const_iterator it;
170 std::list<Counter*>::const_iterator it;
194 (marker >> 8) & 0xff, counter->
count());
200 std::list<Counter*>::const_iterator it;
202 if (strcmp((*it)->name(),
name) == 0) {
209 static const char* error_message =
210 "# Error: Unknown counter \"%s\". Exiting.\n";
211 fprintf(stderr, error_message,
name);
218 std::list<Counter*>::iterator it;
226 std::list<Counter*>::iterator it;
233 void Instrument::VisitPCRelAddressing(
Instruction* instr) {
240 void Instrument::VisitAddSubImmediate(Instruction* instr) {
246 (instr->Rd() == 31) && (instr->Rn() == 31)) {
248 sp_counter->Increment();
250 add_sub_counter->Increment();
255 void Instrument::VisitLogicalImmediate(Instruction* instr) {
257 static Counter* counter =
GetCounter(
"Logical DP");
258 counter->Increment();
262 void Instrument::VisitMoveWideImmediate(Instruction* instr) {
264 static Counter* counter =
GetCounter(
"Move Immediate");
267 unsigned imm = instr->ImmMoveWide();
270 counter->Increment();
275 void Instrument::VisitBitfield(Instruction* instr) {
277 static Counter* counter =
GetCounter(
"Other Int DP");
278 counter->Increment();
282 void Instrument::VisitExtract(Instruction* instr) {
284 static Counter* counter =
GetCounter(
"Other Int DP");
285 counter->Increment();
289 void Instrument::VisitUnconditionalBranch(Instruction* instr) {
291 static Counter* counter =
GetCounter(
"Unconditional Branch");
292 counter->Increment();
296 void Instrument::VisitUnconditionalBranchToRegister(Instruction* instr) {
298 static Counter* counter =
GetCounter(
"Unconditional Branch");
299 counter->Increment();
303 void Instrument::VisitCompareBranch(Instruction* instr) {
305 static Counter* counter =
GetCounter(
"Compare and Branch");
306 counter->Increment();
310 void Instrument::VisitTestBranch(Instruction* instr) {
312 static Counter* counter =
GetCounter(
"Test and Branch");
313 counter->Increment();
317 void Instrument::VisitConditionalBranch(Instruction* instr) {
319 static Counter* counter =
GetCounter(
"Conditional Branch");
320 counter->Increment();
324 void Instrument::VisitSystem(Instruction* instr) {
326 static Counter* counter =
GetCounter(
"Other");
327 counter->Increment();
331 void Instrument::VisitException(Instruction* instr) {
333 static Counter* counter =
GetCounter(
"Other");
334 counter->Increment();
349 void Instrument::VisitLoadStorePairPostIndex(
Instruction* instr) {
355 void Instrument::VisitLoadStorePairOffset(Instruction* instr) {
361 void Instrument::VisitLoadStorePairPreIndex(Instruction* instr) {
367 void Instrument::VisitLoadStorePairNonTemporal(Instruction* instr) {
373 void Instrument::VisitLoadLiteral(Instruction* instr) {
375 static Counter* counter =
GetCounter(
"Load Literal");
376 counter->Increment();
390 case STR_x: store_int_counter->
Increment();
break;
392 case STR_d: store_fp_counter->
Increment();
break;
401 case LDRSH_w: load_int_counter->
Increment();
break;
403 case LDR_d: load_fp_counter->
Increment();
break;
409 void Instrument::VisitLoadStoreUnscaledOffset(
Instruction* instr) {
415 void Instrument::VisitLoadStorePostIndex(Instruction* instr) {
421 void Instrument::VisitLoadStorePreIndex(Instruction* instr) {
427 void Instrument::VisitLoadStoreRegisterOffset(Instruction* instr) {
433 void Instrument::VisitLoadStoreUnsignedOffset(Instruction* instr) {
439 void Instrument::VisitLogicalShifted(Instruction* instr) {
441 static Counter* counter =
GetCounter(
"Logical DP");
442 counter->Increment();
446 void Instrument::VisitAddSubShifted(Instruction* instr) {
448 static Counter* counter =
GetCounter(
"Add/Sub DP");
449 counter->Increment();
453 void Instrument::VisitAddSubExtended(Instruction* instr) {
455 static Counter* sp_counter =
GetCounter(
"SP Adjust");
456 static Counter* add_sub_counter =
GetCounter(
"Add/Sub DP");
459 (instr->Rd() == 31) && (instr->Rn() == 31)) {
461 sp_counter->Increment();
463 add_sub_counter->Increment();
468 void Instrument::VisitAddSubWithCarry(Instruction* instr) {
470 static Counter* counter =
GetCounter(
"Add/Sub DP");
471 counter->Increment();
475 void Instrument::VisitConditionalCompareRegister(Instruction* instr) {
477 static Counter* counter =
GetCounter(
"Conditional Compare");
478 counter->Increment();
482 void Instrument::VisitConditionalCompareImmediate(Instruction* instr) {
484 static Counter* counter =
GetCounter(
"Conditional Compare");
485 counter->Increment();
489 void Instrument::VisitConditionalSelect(Instruction* instr) {
491 static Counter* counter =
GetCounter(
"Conditional Select");
492 counter->Increment();
496 void Instrument::VisitDataProcessing1Source(Instruction* instr) {
498 static Counter* counter =
GetCounter(
"Other Int DP");
499 counter->Increment();
503 void Instrument::VisitDataProcessing2Source(Instruction* instr) {
505 static Counter* counter =
GetCounter(
"Other Int DP");
506 counter->Increment();
510 void Instrument::VisitDataProcessing3Source(Instruction* instr) {
512 static Counter* counter =
GetCounter(
"Other Int DP");
513 counter->Increment();
517 void Instrument::VisitFPCompare(Instruction* instr) {
519 static Counter* counter =
GetCounter(
"FP DP");
520 counter->Increment();
524 void Instrument::VisitFPConditionalCompare(Instruction* instr) {
526 static Counter* counter =
GetCounter(
"Conditional Compare");
527 counter->Increment();
531 void Instrument::VisitFPConditionalSelect(Instruction* instr) {
533 static Counter* counter =
GetCounter(
"Conditional Select");
534 counter->Increment();
538 void Instrument::VisitFPImmediate(Instruction* instr) {
540 static Counter* counter =
GetCounter(
"FP DP");
541 counter->Increment();
545 void Instrument::VisitFPDataProcessing1Source(Instruction* instr) {
547 static Counter* counter =
GetCounter(
"FP DP");
548 counter->Increment();
552 void Instrument::VisitFPDataProcessing2Source(Instruction* instr) {
554 static Counter* counter =
GetCounter(
"FP DP");
555 counter->Increment();
559 void Instrument::VisitFPDataProcessing3Source(Instruction* instr) {
561 static Counter* counter =
GetCounter(
"FP DP");
562 counter->Increment();
566 void Instrument::VisitFPIntegerConvert(Instruction* instr) {
568 static Counter* counter =
GetCounter(
"FP DP");
569 counter->Increment();
573 void Instrument::VisitFPFixedPointConvert(Instruction* instr) {
575 static Counter* counter =
GetCounter(
"FP DP");
576 counter->Increment();
580 void Instrument::VisitUnallocated(Instruction* instr) {
582 static Counter* counter =
GetCounter(
"Other");
583 counter->Increment();
587 void Instrument::VisitUnimplemented(Instruction* instr) {
589 static Counter* counter =
GetCounter(
"Other");
590 counter->Increment();
char name_[kCounterNameMaxLength]
Counter(const char *name, CounterType type=Gauge)
Instr Mask(uint32_t mask) const
void HandleInstrumentationEvent(unsigned event)
void DumpEventMarker(unsigned marker)
std::list< Counter * > counters_
Counter * GetCounter(const char *name)
Instrument(const char *datafile=NULL, uint64_t sample_period=kDefaultInstrumentationSamplingPeriod)
void InstrumentLoadStore(Instruction *instr)
void InstrumentLoadStorePair(Instruction *instr)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
static const CounterDescriptor kCounterList[]
const int kCounterNameMaxLength
const unsigned kZeroRegCode
Debugger support for the V8 JavaScript engine.