54 void FastNewClosureDescriptor::Initialize(CallInterfaceDescriptorData* data) {
55 Register registers[] = {
cp,
r2};
60 void FastNewContextDescriptor::Initialize(CallInterfaceDescriptorData* data) {
61 Register registers[] = {
cp,
r1};
66 void ToNumberDescriptor::Initialize(CallInterfaceDescriptorData* data) {
67 Register registers[] = {
cp,
r0};
72 void NumberToStringDescriptor::Initialize(CallInterfaceDescriptorData* data) {
73 Register registers[] = {
cp,
r0};
78 void FastCloneShallowArrayDescriptor::Initialize(
79 CallInterfaceDescriptorData* data) {
80 Register registers[] = {
cp,
r3,
r2,
r1};
81 Representation representations[] = {
88 void FastCloneShallowObjectDescriptor::Initialize(
89 CallInterfaceDescriptorData* data) {
95 void CreateAllocationSiteDescriptor::Initialize(
96 CallInterfaceDescriptorData* data) {
97 Register registers[] = {
cp,
r2,
r3};
102 void StoreArrayLiteralElementDescriptor::Initialize(
103 CallInterfaceDescriptorData* data) {
104 Register registers[] = {
cp,
r3,
r0};
109 void CallFunctionDescriptor::Initialize(CallInterfaceDescriptorData* data) {
110 Register registers[] = {
cp,
r1};
115 void CallFunctionWithFeedbackDescriptor::Initialize(
116 CallInterfaceDescriptorData* data) {
117 Register registers[] = {
cp,
r1,
r3};
125 void CallConstructDescriptor::Initialize(CallInterfaceDescriptorData* data) {
133 Register registers[] = {
cp,
r0,
r1,
r2};
138 void RegExpConstructResultDescriptor::Initialize(
139 CallInterfaceDescriptorData* data) {
140 Register registers[] = {
cp,
r2,
r1,
r0};
145 void TransitionElementsKindDescriptor::Initialize(
146 CallInterfaceDescriptorData* data) {
147 Register registers[] = {
cp,
r0,
r1};
152 void ArrayConstructorConstantArgCountDescriptor::Initialize(
153 CallInterfaceDescriptorData* data) {
159 Register registers[] = {
cp,
r1,
r2};
164 void ArrayConstructorDescriptor::Initialize(CallInterfaceDescriptorData* data) {
166 Register registers[] = {
cp,
r1,
r2,
r0};
167 Representation representations[] = {
174 void InternalArrayConstructorConstantArgCountDescriptor::Initialize(
175 CallInterfaceDescriptorData* data) {
180 Register registers[] = {
cp,
r1};
185 void InternalArrayConstructorDescriptor::Initialize(
186 CallInterfaceDescriptorData* data) {
188 Register registers[] = {
cp,
r1,
r0};
196 void CompareNilDescriptor::Initialize(CallInterfaceDescriptorData* data) {
197 Register registers[] = {
cp,
r0};
202 void ToBooleanDescriptor::Initialize(CallInterfaceDescriptorData* data) {
203 Register registers[] = {
cp,
r0};
208 void BinaryOpDescriptor::Initialize(CallInterfaceDescriptorData* data) {
209 Register registers[] = {
cp,
r1,
r0};
214 void BinaryOpWithAllocationSiteDescriptor::Initialize(
215 CallInterfaceDescriptorData* data) {
216 Register registers[] = {
cp,
r2,
r1,
r0};
221 void StringAddDescriptor::Initialize(CallInterfaceDescriptorData* data) {
222 Register registers[] = {
cp,
r1,
r0};
227 void KeyedDescriptor::Initialize(CallInterfaceDescriptorData* data) {
228 static PlatformInterfaceDescriptor noInlineDescriptor =
231 Register registers[] = {
235 Representation representations[] = {
240 &noInlineDescriptor);
244 void NamedDescriptor::Initialize(CallInterfaceDescriptorData* data) {
245 static PlatformInterfaceDescriptor noInlineDescriptor =
248 Register registers[] = {
252 Representation representations[] = {
257 &noInlineDescriptor);
261 void CallHandlerDescriptor::Initialize(CallInterfaceDescriptorData* data) {
262 static PlatformInterfaceDescriptor default_descriptor =
265 Register registers[] = {
269 Representation representations[] = {
274 &default_descriptor);
278 void ArgumentAdaptorDescriptor::Initialize(CallInterfaceDescriptorData* data) {
279 static PlatformInterfaceDescriptor default_descriptor =
282 Register registers[] = {
288 Representation representations[] = {
295 &default_descriptor);
299 void ApiFunctionDescriptor::Initialize(CallInterfaceDescriptorData* data) {
300 static PlatformInterfaceDescriptor default_descriptor =
303 Register registers[] = {
310 Representation representations[] = {
318 &default_descriptor);
static const Register function_address()
static const Register parameter_count()
static const Register index()
void Initialize(int register_parameter_count, Register *registers, Representation *param_representations, PlatformInterfaceDescriptor *platform_descriptor=NULL)
static const Register ContextRegister()
const CallInterfaceDescriptorData * data() const
static const Register MapRegister()
static const Register left()
static const Register right()
static const Register ReceiverRegister()
static const Register NameRegister()
static const Register exponent()
static const Register exponent()
static Representation External()
static Representation Smi()
static Representation Integer32()
static Representation Tagged()
static const Register ReceiverRegister()
static const Register NameRegister()
static const Register ValueRegister()
static const Register VectorRegister()
static const Register SlotRegister()
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
@ CAN_INLINE_TARGET_ADDRESS
@ NEVER_INLINE_TARGET_ADDRESS
Debugger support for the V8 JavaScript engine.