37 #ifndef V8_IA32_ASSEMBLER_IA32_INL_H_
38 #define V8_IA32_ASSEMBLER_IA32_INL_H_
56 void RelocInfo::apply(intptr_t delta,
ICacheFlushMode icache_flush_mode) {
89 Address RelocInfo::target_address() {
95 Address RelocInfo::target_address_address() {
103 Address RelocInfo::constant_pool_entry_address() {
109 int RelocInfo::target_address_size() {
114 void RelocInfo::set_target_address(
Address target,
123 host(),
this, HeapObject::cast(target_code));
128 Object* RelocInfo::target_object() {
134 Handle<Object> RelocInfo::target_object_handle(Assembler* origin) {
140 void RelocInfo::set_target_object(
Object* target,
150 target->IsHeapObject()) {
157 Address RelocInfo::target_reference() {
163 Address RelocInfo::target_runtime_entry(Assembler* origin) {
169 void RelocInfo::set_target_runtime_entry(
Address target,
173 if (target_address() != target) {
174 set_target_address(target, write_barrier_mode, icache_flush_mode);
179 Handle<Cell> RelocInfo::target_cell_handle() {
182 return Handle<Cell>(
reinterpret_cast<Cell**
>(address));
186 Cell* RelocInfo::target_cell() {
192 void RelocInfo::set_target_cell(Cell* cell,
210 Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) {
217 Code* RelocInfo::code_age_stub() {
225 void RelocInfo::set_code_age_stub(Code* stub,
234 Address RelocInfo::call_address() {
241 void RelocInfo::set_call_address(
Address target) {
248 host(),
this, HeapObject::cast(target_code));
253 Object* RelocInfo::call_object() {
254 return *call_object_address();
258 void RelocInfo::set_call_object(
Object* target) {
259 *call_object_address() = target;
263 Object** RelocInfo::call_object_address() {
266 return reinterpret_cast<Object**
>(
pc_ + 1);
270 void RelocInfo::WipeOut() {
282 bool RelocInfo::IsPatchedReturnSequence() {
287 bool RelocInfo::IsPatchedDebugBreakSlotSequence() {
295 visitor->VisitEmbeddedPointer(
this);
298 visitor->VisitCodeTarget(
this);
300 visitor->VisitCell(
this);
302 visitor->VisitExternalReference(
this);
305 visitor->VisitCodeAgeSequence(
this);
307 IsPatchedReturnSequence()) ||
309 IsPatchedDebugBreakSlotSequence())) &&
310 isolate->debug()->has_break_points()) {
311 visitor->VisitDebugTarget(
this);
313 visitor->VisitRuntimeEntry(
this);
318 template<
typename StaticVisitor>
322 StaticVisitor::VisitEmbeddedPointer(heap,
this);
325 StaticVisitor::VisitCodeTarget(heap,
this);
327 StaticVisitor::VisitCell(heap,
this);
329 StaticVisitor::VisitExternalReference(
this);
332 StaticVisitor::VisitCodeAgeSequence(heap,
this);
333 }
else if (heap->isolate()->debug()->has_break_points() &&
335 IsPatchedReturnSequence()) ||
337 IsPatchedDebugBreakSlotSequence()))) {
338 StaticVisitor::VisitDebugTarget(heap,
this);
340 StaticVisitor::VisitRuntimeEntry(
this);
353 x_ =
reinterpret_cast<int32_t>(ext.address());
359 x_ =
reinterpret_cast<int32_t>(internal_offset);
368 if (obj->IsHeapObject()) {
369 DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj));
370 x_ =
reinterpret_cast<intptr_t
>(
handle.location());
374 x_ =
reinterpret_cast<intptr_t
>(obj);
381 x_ =
reinterpret_cast<intptr_t
>(
value);
387 x_ =
reinterpret_cast<int32_t>(addr);
403 if (obj->IsHeapObject()) {
404 emit(
reinterpret_cast<intptr_t
>(
handle.location()),
408 emit(
reinterpret_cast<intptr_t
>(obj));
428 emit(
reinterpret_cast<intptr_t
>(code.location()), rmode,
id);
434 Label* label =
reinterpret_cast<Label*
>(x.x_);
444 if (label->is_bound()) {
449 emit_disp(label, Displacement::CODE_RELATIVE);
469 ConstantPoolArray* constant_pool,
491 return Displacement(
long_at(
L->pos()));
501 Displacement disp(
L, type);
503 emit(
static_cast<int>(disp.data()));
509 if (
L->is_near_linked()) {
510 int offset =
L->near_link_pos() -
pc_offset();
512 disp =
static_cast<byte>(offset & 0xFF);
519 void Operand::set_modrm(
int mod,
Register rm) {
521 buf_[0] = mod << 6 | rm.
code();
526 void Operand::set_sib(
ScaleFactor scale, Register index, Register base) {
528 DCHECK((scale & -4) == 0);
531 buf_[1] = scale << 6 | index.code() << 3 | base.code();
536 void Operand::set_disp8(int8_t disp) {
537 DCHECK(len_ == 1 || len_ == 2);
538 *
reinterpret_cast<int8_t*
>(&buf_[len_++]) = disp;
543 DCHECK(len_ == 1 || len_ == 2);
557 Register
reg = { xmm_reg.
code() };
565 set_dispr(disp, rmode);
572 set_dispr(imm.x_, imm.rmode_);
Isolate * isolate() const
static const int kSpecialTargetSize
void emit_w(const Immediate &x)
static Address target_address_at(Address pc, ConstantPoolArray *constant_pool)
void disp_at_put(Label *L, Displacement disp)
void emit_code_relative_offset(Label *label)
void emit_disp(Label *L, Displacement::Type type)
static bool IsNop(Instr instr, int type=NON_MARKING_NOP)
void emit_near_disp(Label *L)
void long_at_put(int pos, uint32_t x)
static const int kPatchDebugBreakSlotReturnOffset
static Address break_address_from_return_address(Address pc)
Displacement disp_at(Label *L)
void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data=0)
uint32_t long_at(int pos)
static void set_target_address_at(Address pc, ConstantPoolArray *constant_pool, Address target, ICacheFlushMode icache_flush_mode=FLUSH_ICACHE_IF_NEEDED)
static Address target_address_from_return_address(Address pc)
static const int kCallTargetAddressOffset
static const int kValueOffset
static Cell * FromValueAddress(Address value)
static Code * GetCodeFromTargetAddress(Address address)
byte * instruction_start()
static const int kHeaderSize
static void FlushICache(void *start, size_t size)
static bool SupportsCrankshaft()
IncrementalMarking * incremental_marking()
static Object *& Object_at(Address addr)
static Address & Address_at(Address addr)
static Handle< Object > & Object_Handle_at(Address addr)
Operand(Register reg, Shift shift=LSL, unsigned shift_amount=0)
static bool IsDebugBreakSlot(Mode mode)
static bool IsJSReturn(Mode mode)
static bool IsEmbeddedObject(Mode mode)
static bool IsRuntimeEntry(Mode mode)
static bool IsCodeTarget(Mode mode)
static bool IsNone(Mode mode)
static bool IsExternalReference(Mode mode)
static bool IsInternalReference(Mode mode)
static bool IsCodeAgeSequence(Mode mode)
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long mode(MIPS only)") DEFINE_BOOL(enable_always_align_csp
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
TypeImpl< ZoneTypeConfig > Type
kSerializedDataOffset Object
Handle< T > handle(T *t, Isolate *isolate)
static const byte kCallOpcode
static const int kNoCodeAgeSequenceLength
PerThreadAssertScopeDebugOnly< DEFERRED_HANDLE_DEREFERENCE_ASSERT, true > AllowDeferredHandleDereference
Debugger support for the V8 JavaScript engine.