5 #ifndef V8_REGISTER_ALLOCATOR_H_
6 #define V8_REGISTER_ALLOCATOR_H_
20 class InstructionOperand;
21 class UnallocatedOperand;
249 if (pos !=
NULL)
return pos->
hint();
337 return &fixed_live_ranges_;
340 return &fixed_double_live_ranges_;
353 int vreg = code()->NextVirtualRegister();
355 allocation_ok_ =
false;
493 return code()->InstructionAt(index);
RegisterKind RequiredRegisterKind(int virtual_register) const
ZoneList< LiveRange * > inactive_live_ranges_
ZoneList< LiveRange * > reusable_slots_
bool CanEagerlyResolveControlFlow(BasicBlock *block) const
void InactiveToActive(LiveRange *range)
DISALLOW_COPY_AND_ASSIGN(RegisterAllocator)
bool IsOutputRegisterOf(Instruction *instr, int index)
BitVector * ComputeLiveOut(BasicBlock *block)
bool HasTaggedValue(int virtual_register) const
ZoneList< BitVector * > live_in_sets_
void AddToInactive(LiveRange *range)
void InitializeLivenessAnalysis()
InstructionSequence * code_
void MeetRegisterConstraintsForLastInstructionInBlock(BasicBlock *block)
void ResolvePhis(BasicBlock *block)
LiveRange * FixedLiveRangeFor(int index)
LiveRange * SplitRangeAt(LiveRange *range, LifetimePosition pos)
void AddToUnhandledUnsorted(LiveRange *range)
static void TraceAlloc(const char *msg,...)
ZoneList< LiveRange * > active_live_ranges_
const char * RegisterName(int allocation_index)
void PopulatePointerMaps()
void AddToActive(LiveRange *range)
void AllocateBlockedReg(LiveRange *range)
bool SafePointsAreInOrder() const
BitVector * assigned_double_registers()
static int FixedLiveRangeID(int index)
BitVector * assigned_registers()
void ResolveControlFlow(LiveRange *range, BasicBlock *block, BasicBlock *pred)
InstructionOperand * TryReuseSpillSlot(LiveRange *range)
void SetLiveRangeAssignedRegister(LiveRange *range, int reg)
RegisterAllocator(InstructionSequence *code)
void AddToUnhandledSorted(LiveRange *range)
void Define(LifetimePosition position, InstructionOperand *operand, InstructionOperand *hint)
static int FixedDoubleLiveRangeID(int index)
InstructionSequence * code() const
int RegisterCount() const
void Spill(LiveRange *range)
Instruction * InstructionAt(int index)
LifetimePosition FindOptimalSplitPos(LifetimePosition start, LifetimePosition end)
void AddInitialIntervals(BasicBlock *block, BitVector *live_out)
void SpillAfter(LiveRange *range, LifetimePosition pos)
bool IsOutputDoubleRegisterOf(Instruction *instr, int index)
void AllocateDoubleRegisters()
const Vector< LiveRange * > * fixed_double_live_ranges() const
void SpillBetweenUntil(LiveRange *range, LifetimePosition start, LifetimePosition until, LifetimePosition end)
const ZoneList< LiveRange * > * live_ranges() const
LiveRange * LiveRangeFor(int index)
bool IsBlockBoundary(LifetimePosition pos)
BitVector * assigned_registers_
void ActiveToInactive(LiveRange *range)
void MeetConstraintsBetween(Instruction *first, Instruction *second, int gap_index)
EmbeddedVector< LiveRange *, Register::kMaxNumAllocatableRegisters > fixed_live_ranges_
BasicBlock * GetBlock(LifetimePosition pos)
ZoneList< LiveRange * > unhandled_live_ranges_
LiveRange * SplitBetween(LiveRange *range, LifetimePosition start, LifetimePosition end)
LifetimePosition FindOptimalSpillingPos(LiveRange *range, LifetimePosition pos)
void ProcessInstructions(BasicBlock *block, BitVector *live)
bool TryAllocateFreeReg(LiveRange *range)
BitVector * assigned_double_registers_
const Vector< LiveRange * > * fixed_live_ranges() const
GapInstruction * GetLastGap(BasicBlock *block)
void SplitAndSpillIntersecting(LiveRange *range)
ZoneList< LiveRange * > live_ranges_
void AllocateGeneralRegisters()
ParallelMove * GetConnectingParallelMove(LifetimePosition pos)
EmbeddedVector< LiveRange *, DoubleRegister::kMaxNumAllocatableRegisters > fixed_double_live_ranges_
void ActiveToHandled(LiveRange *range)
void FreeSpillSlot(LiveRange *range)
void AddConstraintsGapMove(int index, InstructionOperand *from, InstructionOperand *to)
void ResolveControlFlow()
void MeetRegisterConstraints(BasicBlock *block)
void SpillBetween(LiveRange *range, LifetimePosition start, LifetimePosition end)
void Use(LifetimePosition block_start, LifetimePosition position, InstructionOperand *operand, InstructionOperand *hint)
LiveRange * LiveRangeFor(InstructionOperand *operand)
void InactiveToHandled(LiveRange *range)
void MeetRegisterConstraints()
InstructionOperand * AllocateFixed(UnallocatedOperand *operand, int pos, bool is_tagged)
LiveRange * FixedDoubleLiveRangeFor(int index)
static LifetimePosition MaxPosition()
static LifetimePosition FromInstructionIndex(int index)
LifetimePosition NextInstruction() const
LifetimePosition InstructionEnd() const
int InstructionIndex() const
bool IsInstructionStart() const
LifetimePosition PrevInstruction() const
static LifetimePosition Invalid()
LifetimePosition(int value)
STATIC_ASSERT(IS_POWER_OF_TWO(kStep))
LifetimePosition InstructionStart() const
UsePosition * first_pos() const
void MakeSpilled(Zone *zone)
bool HasAllocatedSpillOperand() const
void SetSpillStartIndex(int start)
bool is_non_loop_phi() const
void set_assigned_register(int reg, Zone *zone)
void SetSpillOperand(InstructionOperand *operand)
static const int kInvalidAssignment
void ShortenTo(LifetimePosition start)
friend class RegisterAllocator
void set_is_non_loop_phi(bool is_non_loop_phi)
UseInterval * first_interval_
UsePosition * NextRegisterPosition(LifetimePosition start)
InstructionOperand * CreateAssignedOperand(Zone *zone)
LifetimePosition FirstIntersection(LiveRange *other)
UseInterval * current_interval_
int assigned_register() const
InstructionOperand * FirstHint() const
int spill_start_index() const
bool HasRegisterAssigned() const
UsePosition * NextUsePositionRegisterIsBeneficial(LifetimePosition start)
InstructionOperand * current_hint_operand_
UsePosition * PreviousUsePositionRegisterIsBeneficial(LifetimePosition start)
LifetimePosition Start() const
void AddUseInterval(LifetimePosition start, LifetimePosition end, Zone *zone)
UsePosition * NextUsePosition(LifetimePosition start)
void EnsureInterval(LifetimePosition start, LifetimePosition end, Zone *zone)
void ConvertOperands(Zone *zone)
bool CanBeSpilled(LifetimePosition pos)
InstructionOperand * current_hint_operand() const
UsePosition * last_processed_use_
bool ShouldBeAllocatedBefore(const LiveRange *other) const
LiveRange(int id, Zone *zone)
LiveRange * parent() const
UseInterval * last_interval_
void SplitAt(LifetimePosition position, LiveRange *result, Zone *zone)
bool CanCover(LifetimePosition position) const
InstructionOperand * GetSpillOperand() const
bool Covers(LifetimePosition position)
UseInterval * first_interval() const
LifetimePosition End() const
void AddUsePosition(LifetimePosition pos, InstructionOperand *operand, InstructionOperand *hint, Zone *zone)
void set_is_phi(bool is_phi)
void AdvanceLastProcessedMarker(UseInterval *to_start_of, LifetimePosition but_not_past) const
UseInterval * FirstSearchIntervalForPosition(LifetimePosition position) const
InstructionOperand * spill_operand_
RegisterKind Kind() const
unsigned allocator_zone_start_allocation_size_
RegisterAllocatorPhase(const char *name, RegisterAllocator *allocator)
~RegisterAllocatorPhase()
RegisterAllocator * allocator_
DISALLOW_COPY_AND_ASSIGN(RegisterAllocatorPhase)
static const int kMaxVirtualRegisters
LifetimePosition start() const
void set_next(UseInterval *next)
UseInterval(LifetimePosition start, LifetimePosition end)
LifetimePosition Intersect(const UseInterval *other) const
void set_start(LifetimePosition start)
void SplitAt(LifetimePosition pos, Zone *zone)
UseInterval * next() const
LifetimePosition end() const
bool Contains(LifetimePosition point) const
InstructionOperand *const hint_
UsePosition(LifetimePosition pos, InstructionOperand *operand, InstructionOperand *hint)
bool RegisterIsBeneficial() const
bool register_beneficial_
UsePosition * next() const
void set_next(UsePosition *next)
InstructionOperand *const operand_
LifetimePosition pos() const
LifetimePosition const pos_
bool RequiresRegister() const
InstructionOperand * hint() const
InstructionOperand * operand() const
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in only print modified registers Trace simulator debug messages Implied by trace sim abort randomize hashes to avoid predictable hash Fixed seed to use to hash property Print the time it takes to deserialize the snapshot A filename with extra code to be included in the A file to write the raw snapshot bytes to(mksnapshot only)") DEFINE_STRING(raw_context_file
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be expose gc extension under the specified name show built in functions in stack traces use random jit cookie to mask large constants minimum length for automatic enable preparsing CPU profiler sampling interval in microseconds trace out of bounds accesses to external arrays default size of stack region v8 is allowed to maximum length of function source code printed in a stack trace min size of a semi the new space consists of two semi spaces print one trace line following each garbage collection do not print trace line after scavenger collection print cumulative GC statistics in name
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK(condition)
#define IS_POWER_OF_TWO(x)
static LifetimePosition Min(LifetimePosition a, LifetimePosition b)
Debugger support for the V8 JavaScript engine.