5 #ifndef V8_COMPILER_INSTRUCTION_SELECTOR_IMPL_H_
6 #define V8_COMPILER_INSTRUCTION_SELECTOR_IMPL_H_
48 return ConstantOperand::Create(node->id(),
zone());
95 return ImmediateOperand::Create(index,
zone());
126 int index =
sequence()->AddImmediate(Constant(imm));
127 return ImmediateOperand::Create(index,
zone());
144 switch (node->opcode()) {
145 case IrOpcode::kInt32Constant:
146 return Constant(OpParameter<int32_t>(node));
147 case IrOpcode::kInt64Constant:
148 return Constant(OpParameter<int64_t>(node));
149 case IrOpcode::kFloat32Constant:
150 return Constant(OpParameter<float>(node));
151 case IrOpcode::kFloat64Constant:
152 case IrOpcode::kNumberConstant:
153 return Constant(OpParameter<double>(node));
154 case IrOpcode::kExternalConstant:
155 return Constant(OpParameter<ExternalReference>(node));
156 case IrOpcode::kHeapConstant:
162 return Constant(
static_cast<int32_t>(0));
208 class FlagsContinuation
FINAL {
215 BasicBlock* false_block)
217 condition_(condition),
218 true_block_(true_block),
219 false_block_(false_block) {
226 : mode_(
kFlags_set), condition_(condition), result_(result) {
257 switch (condition_) {
307 bool negate = condition_ ==
kEqual;
308 condition_ = condition;
309 if (negate) Negate();
static uint32_t encode(T value)
Isolate * isolate() const
FlagsContinuation(FlagsCondition condition, Node *result)
InstructionCode Encode(InstructionCode opcode)
FlagsCondition condition_
FlagsContinuation(FlagsCondition condition, BasicBlock *true_block, BasicBlock *false_block)
void OverwriteAndNegateIfEqual(FlagsCondition condition)
BasicBlock * false_block_
BasicBlock * true_block() const
BasicBlock * false_block() const
FlagsCondition condition() const
size_t GetTotalSize() const
static const int16_t ANY_REGISTER
InstructionSelector * selector() const
UnallocatedOperand * ToUnallocatedOperand(LinkageLocation location, MachineType type)
static Constant ToConstant(const Node *node)
InstructionOperand * UseImmediate(Node *node)
UnallocatedOperand * Use(Node *node, UnallocatedOperand *operand)
InstructionOperand * TempDoubleRegister()
InstructionOperand * UseLocation(Node *node, LinkageLocation location, MachineType type)
InstructionOperand * DefineAsConstant(Node *node)
InstructionOperand * TempRegister()
InstructionOperand * Use(Node *node)
InstructionOperand * UseFixed(Node *node, Register reg)
UnallocatedOperand * Define(Node *node, UnallocatedOperand *operand)
InstructionOperand * UseUnique(Node *node)
Isolate * isolate() const
InstructionOperand * DefineAsRegister(Node *node)
InstructionOperand * UseRegister(Node *node)
InstructionOperand * UseFixed(Node *node, DoubleRegister reg)
InstructionOperand * DefineSameAsFirst(Node *result)
InstructionOperand * DefineAsFixed(Node *node, Register reg)
InstructionOperand * TempImmediate(int32_t imm)
InstructionSequence * sequence() const
InstructionOperand * DefineAsFixed(Node *node, DoubleRegister reg)
InstructionOperand * Label(BasicBlock *block)
OperandGenerator(InstructionSelector *selector)
InstructionOperand * UseUniqueRegister(Node *node)
InstructionSelector * selector_
InstructionOperand * TempRegister(Register reg)
InstructionOperand * DefineAsLocation(Node *node, LinkageLocation location, MachineType type)
void set_virtual_register(unsigned id)
int virtual_register() const
enable harmony numeric enable harmony object literal extensions Optimize object Array DOM strings and string trace pretenuring decisions of HAllocate instructions Enables optimizations which favor memory size over execution speed maximum source size in bytes considered for a single inlining maximum cumulative number of AST nodes considered for inlining trace the tracking of allocation sites deoptimize every n garbage collections perform array bounds checks elimination analyze liveness of environment slots and zap dead values flushes the cache of optimized code for closures on every GC allow uint32 values on optimize frames if they are used only in safe operations track concurrent recompilation artificial compilation delay in ms do not emit check maps for constant values that have a leaf deoptimize the optimized code if the layout of the maps changes enable context specialization in TurboFan execution budget before interrupt is triggered max percentage of megamorphic generic ICs to allow optimization enable use of SAHF instruction if enable use of VFP3 instructions if available enable use of NEON instructions if enable use of SDIV and UDIV instructions if enable use of MLS instructions if enable loading bit constant by means of movw movt instruction enable unaligned accesses for enable use of d16 d31 registers on ARM this requires VFP3 force all emitted branches to be in long enable alignment of csp to bytes on platforms which prefer the register to always be NULL
#define DCHECK_NOT_NULL(p)
#define DCHECK(condition)
Matcher< Node * > IsBranch(const Matcher< Node * > &value_matcher, const Matcher< Node * > &control_matcher)
MachineType RepresentationOf(MachineType machine_type)
@ kSignedGreaterThanOrEqual
@ kUnsignedLessThanOrEqual
@ kUnorderedGreaterThanOrEqual
@ kUnsignedGreaterThanOrEqual
@ kUnorderedLessThanOrEqual
static const T & OpParameter(const Node *node)
Handle< T > handle(T *t, Isolate *isolate)
Debugger support for the V8 JavaScript engine.
static int ToAllocationIndex(DwVfpRegister reg)
static int ToAllocationIndex(Register reg)
CallDescriptor * descriptor
size_t frame_state_count() const
size_t input_count() const
CallBuffer(Zone *zone, CallDescriptor *descriptor, FrameStateDescriptor *frame_state)
size_t frame_state_value_count() const
InstructionOperandVector instruction_args
InstructionOperandVector outputs
FrameStateDescriptor * frame_state_descriptor